Hutchison Algorithm
4.13 Modified Sine-Phase Difference Approach (Parabolic Approximation)
In this approach, a parabola is used to approximate the sinusoid of the sine half period [62].
Such a parabola may be expressed as
y(4>) = ( 4 <7 ) / 7 r ) ( l - 4>/TT) forO < <f> < n.
Figure 4.26 compares the values that would need to be stored in the ROM. The ideal sine function is represented by a solid line. The dotted line corresponds to the values that are stored in the ROM for the sine phase difference algorithm, and the dashed line corresponds to the values stored in the ROM for the parabola approximation algorithm. This figure shows that to generate the same sine wave, the sine parabola difference approximation uses a more narrow range of values than the sine phase difference approximation, and thus the parabola techniques have fewer storage requirements for a given approximation accuracy.
The parabola approximation technique saves as many as four bits of the memory word length compared to just two bits of saving with the simple sine-phase algorithm. The addition hardware implementation to generate the corresponding parabola values at the ROM output and to add these values to the values retrieved from the ROM can be easily implemented without introducing significant complexity or power drain.
Figure 4.26: Comparison of Sine Phase Difference (Dotted) and Sine Parabola Difference (Dashed) Values.
Section 4.13 Modified Sine-Phase Difference Approach (Parabolic Approximation) 165
Example: Qualcomm's Q2240 Direct Digital Synthesizer
The Q2240 is a product family of direct digital synthesizers that are ideally suited for the needs of wireless communications and complex waveform synthesis [63]. The series consists of three different versions: Q2240I-1N, Q2240I-2S1, and Q2240I-3S1. Each has slightly different frequency resolution, clock speeds, supply voltages, and control inter-faces. The Q2240I-3S1, abbreviated as -3S1, is most versatile and is described here.
The -3S1 can be clocked at a maximum frequency of 100 MHz if using a supply voltage of 5 V and at a maximum frequency of 60 MHz if using a supply voltage of 3.3 V. However, the outputs of the -3S1 operating at 3.3 V can directly drive the inputs of 5V transistor transitor logic (TTL) interfaces.
Figure 4.27 shows the block diagram of the -3S1 synthesizer, which consists of a thirty-one-bit frequency control register (FCR), a thirty-two-bit phase accumulator, and a twelve-bit sine LUT. The value of the FCR is loaded by a parallel interface. The latched FCR value is then accumulated in the phase accumulator at each system clock cycle. The accumulated sine value is passed to the LUT to give a sine amplitude, which is sent to the parallel outputs. The fourteen MSBs of the phase accumulator are used to address the LUT giving an output phase resolution of fourteen bits or an output resolution of twelve bits.
S Y S C L K
F C R
P h a s e A c c u m u l a t o r
S i n e L U T
&
A R B E N M u x
O U T [ 1 : 0 ] ; [ 1 3 . 0 ]
Figure 4.27: Block Diagram of Q2240I-3S1.
SOURCE: Qualcomm, "Synthesizer Products Data Book, Qualcomm ASIC Products" [63].
© Qualcomm, Inc., 1997. Used by Permission.
166 Digital Generation of Signals Chapter 4
A l l the inputs to the FCR are available externally except the MSB, which is internally set to 0. The value of the FCR is loaded by a parallel interface, which can be either synchronous or asynchronous. Using synchronous loading of the parallel inputs allows frequency changes as fast as the system clock frequency, giving a maximum switching frequency of 100 MHz.
The format of the output of the LUT can be set by the user as offset binary two's complement or signed magnitude. The -3S1 also has the capability of generating arbitrary waveforms. The LUT can be bypassed, sending the fourteen MSBs of the phase accumu-lator directly to the parallel outputs. The unused sine LUT is deactivated to reduce power consumption.
The -3S1 also has a power-down mode, which is used to minimize power consumption when the DDS is not used. When the power-down mode is activated, all internal registers will retain their values prior to power-down and the DDS output. The parallel interface is disabled, and no new FCR value can be loaded into the FCR. Thus, when power-down is
enabled, phase continuity is maintained. •
4 . 1 4 Conclusion
DDS provides the flexibility that a software radio needs to support various modulation formats. DDS techniques have many benefits over analog approaches beyond flexibility, including fine frequency resolution; fast response time; easy of manufacturing and testing;
and robustness to environmental and age variations.
Most DDS techniques involve the use of a counting accumulator that drives a ROM to create a periodic digital signal that drives an DAC. The accumulator contents can be altered to produce phase or frequency modulation and the output of the ROM can be changed to impart amplitude modulation.
Issues in DDS design, such as spectral purity, can be addressed though phase random-ization procedures or by using simple PLLs to filter spurious signals. ROM size constraints can be overcome by using compression techniques. Trigonometric identities can be used to greatly reduce the ROM storage requirements or alternatively reduce spurious signals due to limited ROM size. Random sequences with specific statistical features have numerous uses in creating modulated signals.
Section 4.15 Questions 167
4.15 Questions
1. A DDS system is generating a sine wave utilizing the following parameters:
N = 8, W = 6,5 = 8, na = 6, and Fcik = 20 MHz.
Find
(a) the operating frequency, (b) the smallest possible frequency,
(c) the location of the first three spurs due to phase truncation, (d) the location of the first spur due to periodic jitter.
2. What is the drawback of DDS systems and how can hybrid systems help to combat this drawback?
3. Which of the basic approaches is the most reliable in generating a frequency modu-lation (FM) signal?
4. What is the benefit when the Wheatley procedure is introduced in DDS implementa-tion?
5. Find a commercially available DDS chip and describe its operation.
6. Derive Equation 4.8.
7. Derive Equation 4.9.
8. Describe the components of a signal generation system for a WCDMA system in which one must provide a pilot channel of Walsh sequences and a long subscriber sequence with good cross-correlation properties. Include the generation of the analog sinusoidal waveforms, the digital codes, and the modulation of the digital codes onto the analog waveforms.
C h a p t e r 5
A N A L O G T O D I G I T A L A N D D I G I T A L T O A N A L O G
C O N V E R S I O N
J e f f r e y H . R e e d , J a m e s N e e l , a n d S u j a y e e n d a r S a c h i n d a r
5.1 Introduction
The proper selection of data converters, both analog to digital converters (ADCs) and dig-ital to analog converters (DACs), is one of the most challenging steps in designing a soft-ware radio. In many instances, the data converter will be the determining factor for the performance of the overall radio design since the data converter impacts the radio's power consumption, dynamic range, bandwidth, and total cost. The performance of a data con-verter can even affect the design of a receiver structure; better data conversion performance is needed for broadband IF sampling than for a narrowband super-heterodyne receiver. In fact, many use the proximity of the data conversion process to the antenna as a way to judge how close a radio comes to being an ideal software radio [64,65].
In an ideal software radio, the data conversion process occurs immediately after the antenna in the receiver chain. The data converter samples the RF signal and then completes the downconversion process entirely in the digital domain, thus obviating the need for troublesome analog components. Data conversion at RF places some rather extreme device constraints on the data converter: the data converter would need
169
170 Analog t o Digital and Digital t o Analog Conversion Chapter 5
• a very high sampling rate to support wide signal bandwidths,
• a high number of effective quantization bits to support a high dynamic range,
• an operating bandwidth of several GHz to allow the conversion of a signal over a greatly varying (and theoretically arbitrary) range of frequencies,
• a large spurious-free dynamic range to allow for the recovery of small-scale signals in the presence of strong interferers while producing very little distortion,
• an ability to meet these criteria without consuming an excessive amount of power and at a reasonable price.
However, as the reader may have already surmised, these demands exceed the capabilities of currently available technology. While RF conversion receivers (see Section 2.5) do exist that employ analog preselection before the ADC, receivers that perform data conversion at IF are far more prevalent due to fabrication and performance limitations of data converters.
Unlike many other components in a software radio, data converter state-of-the-art fabri-cation technology advances slowly. Because of the limitations of fabrifabri-cation technology, priorities must be set and trade-offs must be made between bandwidth, dynamic range, power consumption, and cost to find an acceptable design solution for not only the data converter, but also for the entire radio.
Figure 5.1 illustrates, at an abstract level, the relationships that exist between some basic parameters of an ADC. Notice that simultaneously working toward a high bandwidth and a wide dynamic range (desirable features) results in increased power consumption and cost (undesirable features), and any design will be limited by fabrication technology.
As with all designs, no gain can be made in one area without sacrificing performance in
Bandwidth
Fabrication Technology Limitation
Dynamic Range
Figure 5.1: Trade-Offs and Limitations of Converter Performance.
Section 5.2 Parameters of Ideal Data Converters 171
another. So when selecting a data converter, the radio designer must be cognizant of how the chosen parameters will impact the overall radio performance, not just one particular aspect of the radio.
This chapter is intended to aid the radio designer in the process of data converter se-lection by addressing some of the typical issues encountered with data converters. The fundamental parameters of the data conversion process—sampling and quantization—are reviewed first (Section 5.2), followed by important practical parameters, such as band-width, spurious-free dynamic range, and power consumption (Section 5.3). Then, tradi-tional techniques employed to improve the performance of data conversion are surveyed (Section 5.4). Next, typical data converter architectures are examined (Section 5.5). The concluding section reviews fundamental limitations of converters and future prospects for converter performance. As different issues, applications, and architectures are presented, the reader should remain alert to the trade-offs being made to ensure that the solution cho-sen for the data converter meets the design requirements of the entire radio within the limits of fabrication technology.