(ncv) value. A controlling value applied to the input of a gate determines the value at the output of the gate alone (i.e. independent of values at other inputs of the gate). The controlling value for AND and NAND gates is 0, and for OR and NOR gates the controlling value is 1. The non-controlling value for a gate is the complement of the controlling value.
Detection of path-delay faults requires a two-pattern test T = {v1, v2} to be applied to the circuit under test. Further details may be found in Chapter 3.
4.2
The nature of transitions
4.2.1 Transition
The classification of path-delay faults is based on an analysis of the way tran- sitions are propagated along the different paths in the circuit. It is therefore important to have a good understanding of how transitions behave on the way through the circuit. A transition should be understood as described in Defini- tion 7.
Definition 7 (Signal transition) A transition at a signal or a gate in a circuit is a single change in the logic level. A transition may be of one of two different types. A signal change from 0 to 1 is called a rising transition, and a signal change from1 to 0 is called a falling transition.
4.2.2 The maximum number of transitions and their position in
time
In order to test a path-delay fault a transition must be applied to the input of the path. Although only one transition is applied to only one input, one might observe several transitions at the output of the path, and at other outputs as well. This effect is caused by fan-out present in the circuit. Figure 4.2 a illustrates how one transition at each of the inputs of a gate might result in two transitions at the output of the gate. Another example is shown in Figure 4.2 b.
The maximum number of transitions that can be observed at the output of a gate is equal to the sum of the maximum number of transitions observable at each input of that gate. One pass through a topologically sorted netlist using this rule will yield the maximum number of potential transitions observable at any gate in the circuit. This is illustrated in Figure 4.2 c where it is assumed that one transition is applied to each input. An interesting observation is that the maximum number of transition observable at the output of the circuit is
38 Classification of path-delay faults a) b) 1 1 2 3 3 6 c)
Figure 4.2: The maximum number of transitions at a gate.
equal to the number of paths in the circuit. However, in practice one will not experience the maximum number of transitions because transitions are often masked (see Figure 4.3) and prevented from further propagation through gates by controlling values on the other gate inputs. The actual number of observed transitions depends on the exact delay of the gates and nets in the circuit under test in addition to its structure and the applied test patterns.
0
Figure 4.3: Masking of transitions.
A transition propagating through a circuit is delayed by an amount equal to the sum of the delays through the gates and nets on the path it is travelling through. An example, using a simple transport delay, is shown in Figure 4.4 a. The circuit contains two paths and a maximum of two transitions may thus be observed at the output o. The first transition stems from the transition propa- gated through the shortest path i − k − o with a delay of 1 unit, and the second transition stems from the transition propagated through the longest path i − j − o with a delay of 2 units. If the delay of a path is increased, the position of the corresponding transition observable at the output will be adjusted with the same amount. This is illustrated in Figure 4.4 b where the longest path is increased by 1 unit.
4.2 The nature of transitions 39 1 i o i/k 1 2 i 1 o j j j o i/k j o t t 0 1 2 3 4 5 0 1 2 3 4 5 k k a) b)
Figure 4.4: Propagation delay through paths.
points in time where transitions might occur at the output of an circuit. Whether or not an transition is observable at the output depends on, as mentioned earlier, both the structure of the circuit, the delay of the paths and the applied test patterns. Figure 4.5 a shows an imagined circuit with 6 paths from the inputs to the output. The delay of the paths is shown in Figure 4.5 b. From this information one can deduce that maximum 1 transition may be observed at the output 1 unit after a transition is applied to the input of the circuit, no transitions may occur after 2 units, a maximum of three transitions may occur after 3 units, and maximum 2 transitions may occur after a delay of 4 units. The observed waveforms at the output of the circuit might thus be similar to the ones shown in Figure 4.5 c for three different two pattern tests vectors.
4.2.3 Hazards
When more than one transition occurs during a short time interval, the transi- tions are referred to as a hazard. There are two types of hazards static and dy- namic. Static hazard is the term used on a group of two rapid transitions from the initial value and back again. There are two types of static hazards static one hazard (also called low going glitch) and static zero hazard (also called high going glitch). The hazard is called a static one hazard when the initial signal value is 0 followed by a 0 → 1 transition and a 1 → 0 transition. The hazard is called a static zero hazard when the initial signal value is 1 followed by a 1 → 0 transition and a 0 → 1 transition. Dynamic hazard is the term used on a group of three rapid transitions from the initial value to the final value, back to the initial value, and back to the final value again.
40 Classification of path-delay faults Circuit with 6 paths delay 0 1 2 3 path count/
max transition count
1 2 3 a) b) t 4 0 1 2 3 4 c)
Figure 4.5: Possible transitions and their location in time.