The SPICE netlist file generated from the design schematics in Electric has the details of all the components and devices used in the schematics of Figure 4.12, page 67, and in the black box schematics of Figure 4.8, page 57. The black box schematics belongs to
relative timing path LUTblue:PREDi−FIREi−. The sweep parameters wid1 and wid2
are the sizes of the driver and load inverters. The file extension is ‘.spi’.
*** SPICE deck for cell RT1_LUTblue_PredFire{sch} from library *LookUpTable_Thesis
*** Created on Wed Jul 21, 2010 21:21:49 *** Last revised on Tue Aug 03, 2010 20:00:26
*** Written on Tue Aug 03, 2010 20:03:17 by Electric *** VLSI Design System, version 9.00d
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF .OPTIONS NOMOD NOPAGE
* Model cards are described in this file:
.include ’/u/mettalag/models/Models_90nm/MOSIS_90nm_header_ARC.hsp’ *** SUBCIRCUIT NMOS-X_20 FROM CELL redSix:NMOS{sch}
.SUBCKT NMOS-X_20 d g s ** GLOBAL gnd
MNMOSf@0 d g s gnd nch W=’60*(1+ABN/sqrt(60*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(60*2)’
.ENDS NMOS-X_20
*** SUBCIRCUIT PMOS-X_1 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_1 d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’6*(1+ABP/sqrt(6*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(6*2)’
*** SUBCIRCUIT NMOS-X_30 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_30 d g s ** GLOBAL gnd MNMOSf@0 d g s gnd nch W=’90*(1+ABN/sqrt(90*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(90*2)’ .ENDS NMOS-X_30
*** SUBCIRCUIT PMOS-X_30 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_30 d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’180*(1+ABP/sqrt(180*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(180*2)’
.ENDS PMOS-X_30
*** SUBCIRCUIT inv-X_30 FROM CELL redSix:inv{sch} .SUBCKT inv-X_30 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_30 XPMOS@0 out in vdd PMOS-X_30 .ENDS inv-X_30
*** SUBCIRCUIT NMOS-X_80 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_80 d g s
** GLOBAL gnd
MNMOSf@0 d g s gnd nch W=’240*(1+ABN/sqrt(240*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(240*2)’
.ENDS NMOS-X_80
*** SUBCIRCUIT PMOS-X_80 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_80 d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’480*(1+ABP/sqrt(480*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(480*2)’
.ENDS PMOS-X_80
*** SUBCIRCUIT inv-X_80 FROM CELL redSix:inv{sch} .SUBCKT inv-X_80 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_80 XPMOS@0 out in vdd PMOS-X_80 .ENDS inv-X_80
*** SUBCIRCUIT NMOS-X_5 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_5 d g s
** GLOBAL gnd
.ENDS NMOS-X_5
*** SUBCIRCUIT PMOS-X_5 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_5 d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’30*(1+ABP/sqrt(30*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(30*2)’
.ENDS PMOS-X_5
*** SUBCIRCUIT inv-X_5 FROM CELL redSix:inv{sch} .SUBCKT inv-X_5 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_5 XPMOS@0 out in vdd PMOS-X_5 .ENDS inv-X_5
*** SUBCIRCUIT NMOS-X_2 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_2 d g s
** GLOBAL gnd
MNMOSf@0 d g s gnd nch W=’6*(1+ABN/sqrt(6*2))’ + L=’2’ DELVTO=’AVT0N/sqrt(6*2)’
.ENDS NMOS-X_2
*** SUBCIRCUIT PMOS-X_2 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_2 d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’12*(1+ABP/sqrt(12*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(12*2)’
.ENDS PMOS-X_2
*** SUBCIRCUIT inv-X_2 FROM CELL redSix:inv{sch} .SUBCKT inv-X_2 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_2 XPMOS@0 out in vdd PMOS-X_2 .ENDS inv-X_2
*** SUBCIRCUIT NMOS-X_10 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_10 d g s
** GLOBAL gnd
MNMOSf@0 d g s gnd nch W=’30*(1+ABN/sqrt(30*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(30*2)’
.ENDS NMOS-X_10
*** SUBCIRCUIT PMOS-X_20 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_20 d g s
MPMOSf@0 d g s vdd pch W=’120*(1+ABP/sqrt(120*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(120*2)’
.ENDS PMOS-X_20
*** SUBCIRCUIT pms2-X_10 FROM CELL redSix:pms2{sch} .SUBCKT pms2-X_10 d g g2
** GLOBAL vdd
XPMOS@0 net@2 g vdd PMOS-X_20 XPMOS@1 d g2 net@2 PMOS-X_20 .ENDS pms2-X_10
*** SUBCIRCUIT nor2-X_10 FROM CELL redSix:nor2{sch} .SUBCKT nor2-X_10 ina inb out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out ina gnd NMOS-X_10 XNMOS@1 out inb gnd NMOS-X_10 Xpms2@0 out ina inb pms2-X_10 .ENDS nor2-X_10
*** SUBCIRCUIT LUTblue_RT1_path FROM CELL LUTblue_RT1_path{sch} .SUBCKT LUTblue_RT1_path fire pred
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 NMOS@0_d fire gnd NMOS-X_20 XPMOS@0 net@57 net@2 vdd PMOS-X_1 XPMOS@1 net@57 fire net@4 PMOS-X_1
EVCVS@0 net@13 gnd vcvs net@9 gnd 1 max=’10V’ min=’-10V’ Xinv@0 net@20 net@19 inv-X_30
Xinv@1 net@19 fire inv-X_80 Xinv@2 pred net@9 inv-X_5 Xinv@4 net@4 net@2 inv-X_2
Xnor2n@0 net@13 net@9 net@20 nor2-X_10
* Spice Code nodes in cell cell ’LUTblue_RT1_path{sch}’ .ic succ=0v net@68=1v
.ENDS LUTblue_RT1_path
*** SUBCIRCUIT NMOS-X_wid1 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_wid1 d g s
** GLOBAL gnd
MNMOSf@0 d g s gnd nch W=’3*wid1*(1+ABN/sqrt(3*wid1*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(3*wid1*2)’
.ENDS NMOS-X_wid1
*** SUBCIRCUIT PMOS-X_wid1 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_wid1 d g s
+ L=’2’ DELVTO=’AVT0P/sqrt(2*3*wid1*2)’ .ENDS PMOS-X_wid1
*** SUBCIRCUIT inv-X_wid1 FROM CELL redSix:inv{sch} .SUBCKT inv-X_wid1 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_wid1 XPMOS@0 out in vdd PMOS-X_wid1 .ENDS inv-X_wid1
*** SUBCIRCUIT NMOS-X_wids FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_wids d g s ** GLOBAL gnd MNMOSf@0 d g s gnd nch W=’3*(wid1/3)* +(1+ABN/sqrt(3*(wid1/3)*2))’ + L=’2’ DELVTO=’AVT0N/sqrt(3*(wid1/3)*2)’ .ENDS NMOS-X_wids
*** SUBCIRCUIT PMOS-X_wids FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_wids d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’2*3*(wid1/3)*(1+ABP/sqrt(2*3* +(wid1/3)*2))’ L=’2’ DELVTO=’AVT0P/sqrt(2*3*(wid1/3)*2)’ .ENDS PMOS-X_wids
*** SUBCIRCUIT inv-X_wids FROM CELL redSix:inv{sch} .SUBCKT inv-X_wids in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_wids XPMOS@0 out in vdd PMOS-X_wids .ENDS inv-X_wids
*** SUBCIRCUIT NMOS-X_widM FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_widM d g s ** GLOBAL gnd MNMOSf@0 d g s gnd nch W=’3*3*wid2* + (1+ABN/sqrt(3*3*wid2*2))’ + L=’2’ DELVTO=’AVT0N/sqrt(3*3*wid2*2)’ .ENDS NMOS-X_widM
*** SUBCIRCUIT PMOS-X_widM FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_widM d g s
** GLOBAL vdd
MPMOSf@0 d g s vdd pch W=’2*3*3*wid2* +(1+ABP/sqrt(2*3*3*wid2*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(2*3*3*wid2*2)’
*** SUBCIRCUIT inv-X_widM FROM CELL redSix:inv{sch} .SUBCKT inv-X_widM in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_widM XPMOS@0 out in vdd PMOS-X_widM .ENDS inv-X_widM
*** SUBCIRCUIT NMOS-X_wid2 FROM CELL redSix:NMOS{sch} .SUBCKT NMOS-X_wid2 d g s ** GLOBAL gnd MNMOSf@0 d g s gnd nch W=’3*wid2* +(1+ABN/sqrt(3*wid2*2))’ L=’2’ +DELVTO=’AVT0N/sqrt(3*wid2*2)’ .ENDS NMOS-X_wid2
*** SUBCIRCUIT PMOS-X_wid2 FROM CELL redSix:PMOS{sch} .SUBCKT PMOS-X_wid2 d g s ** GLOBAL vdd MPMOSf@0 d g s vdd pch W=’2*3*wid2* +(1+ABP/sqrt(2*3*wid2*2))’ L=’2’ +DELVTO=’AVT0P/sqrt(2*3*wid2*2)’ .ENDS PMOS-X_wid2
*** SUBCIRCUIT inv-X_wid2 FROM CELL redSix:inv{sch} .SUBCKT inv-X_wid2 in out
** GLOBAL gnd ** GLOBAL vdd
XNMOS@0 out in gnd NMOS-X_wid2 XPMOS@0 out in vdd PMOS-X_wid2 .ENDS inv-X_wid2
.global gnd vdd
*** TOP LEVEL CELL: RT1_LUTblue_PredFire{sch} XLUTblue_@0 out[1] in[1] LUTblue_RT1_path
VPulse@0 net@67 gnd pulse 0 ’1v’ ’0ns’ ’50ps’ ’50ps’ ’2ns’ ’4ns’ Xinv@1 Din[1] in[1] inv-X_wid1
Xinv@2 net@67 Din[1] inv-X_wids Xinv@3 net@64 inv@3_out inv-X_widM Xinv@4 out[1] net@64 inv-X_wid2
* Trailer cards are described in this file:
.include ’/u/mettalag/models/Models_90nm/MOSIS_trailer_ARC_1.hsp’ .END