NPSAT-1 PC-104 Interface

The primary purpose of the PC-104 interface module is to handle the actual

transmission and reception of data between the C&DH processor and the experiments

running on CFTP as well as to perform synchronization between clock domains.

Communication between the C&DH processor and CFTP occurs on a bus architecture

running through the PC-104 connectors of the C&DH stack. The bus architecture is a

master/slave configuration with an 11-bit address bus, a 16-bit bi-directional data bus,

and five control lines: bus clock (BCLK), output enable (OE), write enable (WE), chip

select (CS), and interrupt request (IRQ). The C&DH processor acts as master and reads

from and writes to the CFTP PC-104 interface module. CFTP is assigned an address

range of 340h to 34Fh; however, only the even addresses are used since the ARM uses

byte addressing and all transactions are 16-bit. Bus transactions are synchronous with the

51 MHz BCLK; however, due to other modules on the satellite utilizing CS3, read and

write transaction take significantly longer with each containing 16 wait states. The PC-

104 module is able to provide this communication link and synchronization by utilizing

two FSMs interacting with two FIFOs.

The complete FSMs for the PC-104 interface are depicted in Figure 18. After

power on, both the FSMs transition to their idle state. Four types of transactions can be

processed. The FSM on the left hand side handles transactions between the PC-104

interface and the incoming and outgoing FIFOs, while the FSM on the right handles

transactions between the CFTP processors and the incoming and outgoing FIFOs.

The BCLK drives transactions between the C&DH processor and the incoming

and outgoing FIFOs. When an address is received that is in the CFTP’s addressable range

and CS3 goes low, the CFTP flight board is being accessed. The OE control line drops

low when the CFTP is being read from, and the WE control line drops low when the

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CFTP is being written to. In the case of a write, we first transition to the Read C&DH

state where the write enable line of the incoming FIFO is held high for one clock cycle to

capture the data on the PC-104 data bus. To prevent multiple captures, we transition to

the Read Wait C&DH state on the next clock cycle, returning the write enable line of the

incoming FIFO to a low level. Once any of the control signals transitions high or the

address bus transitions out of range, we return to the idle state. Read transactions occur in

a similar fashion except that we first transition to a Hi-Z C&DH state. In this state, we

transition to polarity of the data bus to be able to write to it and send a signal to the bus

transceivers the change their direction as well. The modified direction of the data bus

persists throughout the read transaction. In addition, instead of accessing the write enable

line of the incoming FIFO, we access the read enable line of the outgoing FIFO to

retrieve 16-bits of data to drive on the data bus.

Flow Diagram of the CFTP PC-104 Interface FSM

Figure 18.

The BCLK drives transactions between the C&DH processor and the incoming

and outgoing FIFOs. When an address is received that is in the CFTP’s addressable range

and CS3 goes low, the CFTP flight board is being accessed. The OE control line drops

low when the CFTP is being read from and the WE control line drops low when the

CFTP is being written to. In the case of a write, we first transition to the Read C&DH

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state where the write enable line of the incoming FIFO is held high for one clock cycle to

capture the data on the PC-104 data bus. To prevent multiple captures, we transition to

the Read Wait C&DH state on the next clock cycle, returning the write enable line of the

incoming FIFO to a low level. Once any of the control signals transitions high or the

address bus transitions out of range, we return to the idle state. Read transactions occur in

a similar fashion except that we first transition to a Hi-Z C&DH state. In this state, we

transition to polarity of the data bus to be able to write to it and send a signal to the bus

transceivers the change their direction as well. The modified direction of the data bus

persists throughout the read transaction. In addition, instead of accessing the write enable

line of the incoming FIFO, we access the read enable line of the outgoing FIFO to

retrieve 16 bits of data to drive on the data bus.

The FPGA system clocks drive transactions between the CFTP processors and the

incoming and outgoing FIFOs. A standard four-way handshake is used to move data from

the processors to the outgoing FIFO and to the processors from the incoming FIFO. From

the idle state, either a read or write control signal is raised from the CFTP processors, and

we transition to the read or write state, respectively. In the read state, 32 bits of data are

clocked out from the incoming FIFO and placed on the processor data lines, while in the

write state, the 32 bits of data on the processors data lines are clocked into the outgoing

FIFO. On the following clock cycle from either the read or write state, we transition to

the acknowledge state and signal to the processors that the transaction is complete. When

the processor lowers its read or write signal, for whichever operation it had initially

initiated, the FSM returns to the idle state.

The FIFO are constructed to allow for cross-clock domain synchronization. Both

the read and write ports are clock independent. The synchronization is achieved by

passing through an eight-stage synchronization circuit at the input to the FIFO. While this

does cause a delay for the outputs to be available at the end of the FIFO, the delay is

negligible when compared to the 16 wait states required for every bus transaction. The

FIFO also act as buffers. By utilizing the empty flags on each of the FIFOs, we are able

to produce an interrupt-based system, freeing processor clock cycles since neither

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processor must constantly poll the interface and waste clock cycles when no data is

available for transfer.