The nullor implementations

The required voltage at the input and output of the nullor implementation, and the voltage margins for the bias circuits, determine, together with the actual supply voltage, the maximum voltage swing, at the input and output, respectively. As was pointed out, minimizing

and is favorable for voltage-mode as well as current-mode processing. Therefore, the focus can be on the minimum supply voltage required for a nullor implementation. The difference between this minimum supply voltage required and the actual supply voltage can be used for signal processing.

Nullors can be considered to be comprised of a number of cascaded stages, see figure 3.4. Each stage in turn is realized by means of one or more devices. To obtain the optimum contribution of a stage to the performance of the total nullor implementation, it should be without local feedback [6]; the four chain pa- rameters should be as small as possible. The only stages having this feature are the CE stage for the BJTs and the CS stage for the (MOS)FETs. The CB, CG and CC, CD stages are CE and CS stages with a (non-energetic) local feedback so that they act as a current follower and a voltage follower, respectively.

The devices used for the CE and CS stage require a bias in order to obtain the desired small-signal performance [8]. In figure 3.5 the required bias is depicted for the BJT and the (MOS)FET. For a bipolar transistor this bias is given by: the base-emitter voltage the base current a minimal collector- emitter voltage and the collector current For the MOS(FET) this bias is given by the gate-source voltage the gate current a minimal drain- source voltage and the drain current For the bipolar transistor the four parameters are free to choose with the constraint that two degrees of freedom are available [9]. For the (MOS)FET the gate current is a leakage current and is not free to choose. Therefore, for the (MOS)FET three parameters are free to choose but also with the constraint of two degrees of freedom.

3.3. LOW VOLTAGE 49

As the collector/drain current is most closely related to the behavior of the device (see section 3.4) and the collector-emitter/drain-source voltage is important for the large signal behavior (preventing saturation) it is the most convenient to set these two quantities and let the other(s) be controlled by a loop [8]. Figure 3.6 gives a more practical configuration for realizing the bias (it is depicted for the BJT only). Instead of realizing floating current sources, each current source is split into two sources, each having one terminal grounded.

For this stage the minimum supply voltage required at the input is found to be equal to:

where and are the saturation voltages of the base-current source and the emitter-current source, respectively. At the output the minimum supply

50 CHAPTER 3. LOW-VOLTAGE LOW-POWER DESIGN

voltage required equals:

where is the saturation voltage of the collector-current source. The largest of the two determines the minimum supply voltage required for this stage. In a lot of situations the emitter of the CE stage is grounded and the current source is short circuited and does not need to be realized; consequently, Thus a single floating CE stage requires more supply voltage than the grounded version.

Besides the single CE stage, the balanced version of the CE stage also has small chain parameters. The balancing can be done in two domains [10]:

voltage domain; current domain.

Both these methods are depicted in figure 3.7. Figure 3.7a depicts the balancing in the voltage domain, it is the conventional differential pair. The balancing is a result of the anti-series connection of the inputs (voltage feedback) and the anti-series connection of the outputs of the two transistors. The sum of the two output currents is constant and equal to the tail current. For both transistors the biasing sources as depicted in figure 3.6 are required and thus the minimum supply voltages for the input and output are given by equations (3.3) and (3.4), respectively. Lowering this voltage by grounding the emitters, as was discussed for the single CE stage, is not possible as the balancing then disappears; the series feedback is broken.

For the method as depicted in figure 3.7b it is permissible to have grounded emitters. The two outer transistors are the signal transistors while the two inner transistors determine the sum of the currents through the signal transistors. As

3.3. LOW VOLTAGE 51

a function of the resulting error, a current is fed back so that the sum of the currents of the two signal transistors becomes equal to 2I. Again, balancing is obtained, but now with current feedback. Circuits using this technique are for example [11] and [12]. For this stage the minimum supply voltages for the input and output are also given by equations (3.3) and (3.4), respectively. For this stage, as said, it is permissible to ground the common-emitter node, because the balancing is realized by means of the parallel feedback. Thus this balanced CE stage can have the same minimum supply voltage as the single CE stage. In appendix A, the minimum supply voltage required for the four different types of negative-feedback amplifiers is discussed.