OCSN Application Components

The components of the OCSN application layer are connected to OCSN switches through

OCSN interfaces. All of them have the same basic structure, consisting out of an

OCSN IF and a FSM , processing the incoming data. Figure 8.15 displays this basic

structure. The device has the OCSN physical signal interface as minimum input/output signals. More signal are added according to the application specific hardware part, such as the GPIO pins of a OCSN GPIO device.

The FSM divides into a general and application specific part. The application specific part implements actions for incoming OCSN frames specific to this device, such as reading and writing internal registers or RAM . The general part implements actions for OCSN frames, which are common to all OCSN devices. This includes reactions to

8.2 OCSN 1 while(1) { // c r e a t e the s n a p s h o t , s a v e w h i c h p o r t s h a v e d a t a a v a i l a b l e 3 for(int i =0; i <7; i ++) { s n a p s h o t [ i ]. a v a i l = p o r t [ i ]. d a t a A v a i l ; 5 s n a p s h o t [ i ]. t r a n s m i t t e d =0; } 7 // p u l l f r a m e s f r o m s o u r c e ( s ) to d e s t i n a t i o n ( d ) p o r t s for (int d =0; d <7; d ++) { 9 for (int s =0; s <7; s ++) {

// o n l y do s o m e t h i n g if a f r a m e is a v a i l a b l e and not t r a n s m i t t e d yet

11 if ( s n a p s h o t [ s ]. t r a n s m i t t e d ==0 && s n a p s h o t [ s ]. a v a i l = = 1 ) {

// d e s t i n a t i o n and s o u r c e p o r t are the s a m e and the d e s t .

13 // a d d r e s s is the s a m e as the s w i t c h a d d r e s s of p o r t d

if ( d == s && p o r t [ s ]. f r a m e . dst == switch. a d d r e s s ) {

15 // do s o m e t h i n g a c c o r d i n g to the f r a m e type , d e s t i n a t i o n p o r t and p a y l o a d

// eg . s e n d a p i n g r e s p o n s e

17 } else

// if d e s t i n a t i o n and s o u r c e p o r t d i f f e r and the

19 // d e s t i n a t i o n a d d r e s s is a s u b a d d r of the r e m o t e A d d r of // p o r t d 21 if ( s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d ]. r e m o t e A d d r ))) { // f o r w a r d f r a m e to t h i s p o r t 23 s e n d ( d , p o r t [ s ]. f r a m e ); s n a p s h o t [ s ]. t r a n s m i t t e d =1; 25 } else

// if d is the u p l i n k p o r t and the f r a m e is not d e s t i n e d for any o t h e r p o r t

27 // f o r w a r d it to i if ( u p l i n k ( d ) = = 1 && ( 29 ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 1 % 7 ] . r e m o t e A d d r ) && ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 2 % 7 ] . r e m o t e A d d r ) && 31 ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 3 % 7 ] . r e m o t e A d d r ) && ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 4 % 7 ] . r e m o t e A d d r ) && 33 ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 5 % 7 ] . r e m o t e A d d r ) && ! s u b A d d r ( p o r t [ s ]. f r a m e . dst , p o r t [ d + 6 % 7 ] . r e m o t e A d d r ) 35 ) ) { 37 // f o r w a r d f r a m e to t h i s p o r t s e n d ( d , p o r t [ s ]. f r a m e ); 39 s n a p s h o t [ s ]. t r a n s m i t t e d =1; } 41 } } 43 } // r e m o v e f r a m e s in s n a p s h o t f r o m f i f o q u e u e 45 for(int i =0; i <7; i ++) { if ( s n a p s h o t [ i ]. a v a i l = = 1 ) { 47 s n a p s h o t [ i ]. a v a i l =0; p o r t [ i ]. r e m o v e F r o m Q u e u e (); 49 } } 51 }

8 Implementation of the Multicore Reconfiguration Platform OCSN IF idOCSNdataIN icOCSNctrlIN odOCSNdataOUT odOCSNctrl application specific hardware FSM

Figure 8.15: OCSN application component basic schematic

ICMP ping requests only at the moment. Through ICMP ping requests, the identify of a OCSN component can be determined.

OCSN BRAM device

The VHDL description of the application specific part is very similar to the description of the dual ported block ram, described earlier, but it uses only one port for read and write access. Each of the supported frames, as described in Section 7.2.2, corresponds to a state in the application specific part of the FSM . Data read or written from and to the BRAM has to be encoded into the payload of OCSN frames. The address, to read from or to write to, is also encoded into the payload. The main function of the FSM states is to read the requested number of bytes from the RAM and write them into the payload of the frame, or otherwise round, writing the given number of bytes from the frame to the RAM .

OCSN ICAP device

The ICAP device takes the number of bytes to write and the bytes from an OCSN frame. The FSM always writes 32 bit data words to the ICAP component at 50MHz.

OCSN GPIO device

The GPIO device maps registers to external input and output pins. The FSM takes bytes from an OCSN frame and writes them into internal registers, leading to a change in the GPIO pins. If the status of the input pins is requested, the FSM returns the internal register, connected to these pins.

OCSN PRHS device

The OCSN PRHS device connects the OCSN to the PRHS SoC through a memory mapped input/output interface. The implementation is described by Grebenjuk[37].

8.2 OCSN

OCSN Ethernet Bridge

The OCSN Ethernet Bridge device consist of the basic OCSN device structure, an Ethernet MAC IP core and two synchronised FSMs, for controlling the transmission and reception of data. Figure 8.16 displays both FSMs. The numbers at the beginning of the transition labels set the priority of each transition. They implement a simple synchronisation protocol (shown in Figure 8.17) to ensure, the Ethernet MAC addresses of both endpoints are known to each other.

st_start st_idle st_discover (1)sdRemoteMAC = 000000000000 && scDiscoverTimerInterrupt=1 st_sel_ack (2)sdRemoteMAC /= 000000000000 && srSelectionACKsend=0 st_ocsn (3)scOCSNdataAvail = 1 st_prepare st_send (1)sdTransmitCounter = 0 (2) _{st_wait} scTXdstRDY = 0 (a) Transmission FSM st_start st_idle st_receive scRXsrcRDY=0 && scRXsof=0

(scRXeof =0 && sdReceiveCounter<60)||

(scRXeof = 1 && sdReceiveCounter>60)

st_check1 scRXeof =0 && sdReceiveCounter = 60

st_check2 sdReceivedETH.DST_MAC = idInitialMAC &&

sdReceivedETH.FRAME_TYPE=0x81fc && sdReceivedETH.OCSN_OP=OP_SELECTION

st_send_frame sdReceivedETH.DST_MAC = idInitialMAC &&

sdReceivedETH.FRAME_TYPE=0x81fc && sdReceivedETH.OCSN_OP=OP_OCSN_FRAME scFIFOfull=0

(b) Reception FSM

Figure 8.16: OCSN Ethernet Bridge FSMs

The OCSN2Ethernet bridge starts by sending discovery Ethernet frames through the Ethernet MAC IP core every second. If a host system is available on the other side of the connection or connected to the same Ethernet switch, it answers with a selection frame to the MAC address of the OCSN2Ethernet bridge. The OCSN2Ethernet bridge confirms the reception of the selection frame by sending a selection ack frame.

After this handshake protocol every OCSN frame is encapsulated into an Ethernet frame and transmitted to the remote device. The FSMs do not support answering to

8 Implementation of the Multicore Reconfiguration Platform

Host OCSN2Ethernet

selection discover

selection ack

Figure 8.17: OCSN Ethernet Discovery Protocol

OCSN UART Bridge

Like all application devices, the base of the OCSN UART Bridge is the basic application device structure of Figure 8.15. The application specific hardware consist of a UART component and another FSM , which controls the incoming data from the UART . No special handshake protocol is implemented. The device just starts transmitting through the UART as soon as an OCSN frame arrives and builds an OCSN frame out of the incoming data from the UART . Sending an end of frame byte, identified through the Parity bit, is the only used synchronisation method between local and remote bridge component.