The PC’s parallel port (LPT port) is used to output the display code and control signals for the moving message display.
The parallel port is terminated into a 25-pin D-type female connector at the back of your PC. IBM PCs usually come with one or two LPT ports.
Each parallel port is actually made up of three ports, namely, data port, status port and control port.
Pins 2 through 9 form the 8-bit data port. This is purely a write-only port, which means it can be used only to output data.
Pins 1, 14, 16 and 17 form the control port. This port is read-/write-capable, which means it can be used both for out-puting and inout-puting some data to/from the external hardware.
Pins 10 through 13 and pin 15 to-Fig. 1: Block diagram for moving message display using PC’s parallel port
tabLe i
Parallel-Port Pin Details
Pin number traditional use Port name read/Write Port address Port bit
2-4 Data out Data port W Base D0-D2
5-9 Data out — W Base D3-D7
1 Strobe Control port R/W Base+2 C0
14 Auto feed — R/W Base+2 C1
16 Initialise — R/W Base+2 C2
17 Select input — R/W Base+2 C3
15 Error Status port R Base+1 S3
13 Select — R Base+1 S4
12 Paper end — R Base+1 S5
10 ACK — R Base+1 S6
11 Busy — R Base+1 S7
18-25 Ground — — — —
Parts List Semiconductors:
IC1 - 74LS138 1-of-8 demultiplexer IC2 - 74LS154 1-of-16
demultiplexer IC3, IC4 - 74LS04 hex inverter IC5-IC8 - 74LS244 octal buffer IC9 - 7805 +5V regulator T1-T27 - BC548 npn transistor D1, D2 - 1N4007 rectifier diode Capacitors:
C1 - 1000µF, 25V electrolytic Miscellaneous:
X1 - 230V AC to 7.5V-0-7.5V, 500mA transformer
- 25-pin ‘D’ connector
gether form the status port. This is a read-only port, which means it can be used only to read data from the external hardware.
Table I shows pin details of the
stand-ard parallel port (SPP), including their traditional usage. The base address of the first parallel port (LPT1) is 378 (hex) or 888 (decimal). The data port of the parallel port can be accessed by its base
address. The status port can be accessed using base address+1, i.e. 0379 hex (or 889 decimal). The control port can be accessed using base address+2, i.e. 037A hex (or 890 decimal).
Fig. 2: Circuit diagram for moving message over dot-matrix display
Similar method can be followed for LPT2, whose base address is 0278 in hex.
In the present application, we only need to output data. Since status port is a read-only port, the same is not used. Pins 18 through 25 are grounded.
The circuit
Fig. 1 shows the block diagram of the moving message display. The data to be output from the PC’s parallel port (LPT1) is first processed by the program.
Data lines D0 through D2 of the parallel port are used to enable the seven rows of the dot-matrix display using the 1:8 de-multiplexer (IC1). Data lines D3 through D7 and control lines C0, C1, C2 and C3 are used (as output lines) to enable the columns of the dot-matrix display via the 1:16 demultiplexer (IC2).
Fig. 2 shows the circuit diagram of the moving message display using the PC’s parallel port. The circuit comprises 1-of-8 demultiplexer 74LS138 (IC1), octal tristate buffers 74LS244 (IC5 through IC8), 1-of-16 demultiplexer 74LS154 (IC2), transistors and four 5×7 dot-matrix displays. Discrete light-emitting diodes (LEDs) can also be arranged in a matrix format to make an alphanumeric display, with each diode representing a pixel.
However, it is advantageous to use a 5×7 matrix display which can be obtained in a single package such as FYM-2057IAX from Ningbo Foryard Opti-Electronics Co.
Ltd (refer Fig. 3).
The AC mains is stepped down by transformer X1 to deliver a secondary output of 7.5V-0-7.5V AC at 500 mA. The transformer output is rectified by a full-wave rectifier comprising diodes D1 and Fig. 3: Pin configuration of 5×7 dot-matrix display
Fig. 4: Flow-chart of the program
D2, filtered by capacitor C1, then regu-lated by regulator 7805C (IC9) to provide regulated 5V power supply to the circuit.
1-of-8 demultiplexer 74LS138 (IC1) provides ground path to the cathodes of
all the LEDs of the dot-matrix display through inverters and transistors by using the time-division multiplexing technique.
Pins 1 through 3 of IC1 are connected to pins 2 through 4 of LPT1. The outputs of
IC1 are inverted by NOT gates N1 through N7 and fed to transistors T1 through T7.
IC 74LS138 (IC1) has only eight ac-tive-low outputs. Enable pins E1 and E2 have been made permanently low, while enable pin E3 has been made perma-nently high. Any of the outputs of IC1 can be made low by inputing a 3-bit binary address. The low output of IC1 is made high by the inverter to forward bias the corresponding transistor (T1 through T7).
This provides ground to the cathode of the respective LED of the dot-matrix display as shown in the schematic.
Pins 5 through 9 of LPT1 are connect-ed to the non-inverting input pins of all the tristate buffers 74LS244 (IC5 through IC8). The input data of any buffer becomes available at its output when a low enable signal is provided by IC2. Demultiplexer IC 74LS154 (IC2) provides the enable signal to IC5 through IC8 using time-division multiplexing technique. There is provision for connecting twelve additional 74LS244 ICs to control another twelve 5×7 dot-matrix displays.
IC 74LS154 (IC2) has 16 active-low outputs. Its active-low enable pins E1 and E2 have been made permanently low. Any of the sixteen outputs of IC2 can be made low by inputing a 4-bit binary address.
Output pins 1 through 4 of IC2 are connected to enable pins 1 and 19 of buff-ers IC5 through IC8, respectively. The outputs of IC5 through IC8 are fed to the transistors connected to displays DIS1 through DIS4. The high output of buffer forward biases the connected transistor to provide + 5V supply to the anodes of the corresponding LEDs of the dot-matrix display.
The actual-size, single-side PCB for the moving message over dot-matrix dis-Fig. 5: Diagram of ‘A’ in 5×7 dot-matrix pattern
Fig. 6: Actual-size, single-side PCB for moving message over dot-matrix display
play is shown in Fig. 6 and its component layout in Fig. 7.