Performance of the OSUS circuit





1, if −^π₂ < (2π_N¹n +^2π_Mk + ϕ₁) < ^π₂. 0, if others.

(5.20)

where k represents the index of U and takes values from 0 to M − 1.

Therefore, as can be deduced from Equation 5.20 the advantage of the OSUS method over the DDMTD circuit is the increase in statistics with the factor M , since the OSUS circuit produces M times more measurements than the DDMTD circuit keeping the same time resolution.

5.4.1 Performance of the OSUS circuit

In this section the performance of the OSUS circuit and the DDMTD circuit are compared considering two figures of merit: the measurement rate and the acquisition time.

Measurement Rate

The measurement rate is referred here as the minimum time between two phase measurements. While the phase measurements done with the DDMTD circuit are separated in time a complete period of U^k, the OSUS circuit provides phase measurements separated in time in steps of U^k/M . Thereby, the measurement rate increments by a factor M with respect to the DDMTD. The improvement in the measurement rate could be useful for applications using the DDMTD circuit as part of a control loop.

Acquisition time

On the other hand, the acquisition time refers to the number of Ts periods needed to collect a complete set of measurements. For the DDMTD method the

acquisition time is defined in Equation 5.21.

F t_uc = (K − 1)N T_s+ ∆ϕ_U (5.21)

where K corresponds to the number of samples to be acquired and ∆ϕU is the phase difference between the U signals being compared.

The acquisition time for the OSUS circuit is lower than for the DDMTD circuit. Equation 5.22 refers to the time needed to acquire K samples with an OSUS circuit with M = K.

F t_{OSU S} =K − 1

K N T_s+ ∆ϕ_Uk (5.22)

where ∆ϕ^k_U is the phase difference between the U^k signals being compared.

A comparison between the acquisition time of the DDMTD and the OSUS circuit is presented in Figure 5.10 (a) and (b). Each line represents a different

∆ϕ_U with values between 0.1 · T_U and 0.5 · T_U.

(a) Acquisition time improvement of the OSUS circuit over the DDMTD circuit. Each line represents the acquisition time improve-ment in percentage for M measureimprove-ments vary-ing the factor M. Five ∆ϕ cases are presented taking values from 0.1 · TUto 0.5 · TU.

(b) Comparison between the OSUS circuit and the DDMTD circuit acquisition times.

Each line corresponds to the acquisition time for M measurements. Five ∆ϕ cases are pre-sented taking values from 0.1 · TU to 0.5 · TU.

Figure 5.10: Comparison of the acquisition time of the OSUS and the DDMTD circuit for different phase shifts.

Debouncing techniques

The theoretical resolution of the DDMTD and OSUS circuits is affected by the jitter in the clock signals and metastability in the samplers. During the sampling of the input signals, a high number of glitches are produced in the transition edge of the U^k signals affecting to the precision of the measurements and the transition edge of the U^k. Different debouncing methods to estimate position of the positive edge of U signals were presented in [89] and [90] to mitigate this problem in the DDMTD circuit: First Edge (FE), Positive Edge Median, Zero Count(ZC) and Center-Of-Mass. The debouncing circuit provides a time estimation of the rising edge of the U^k signal.

In this thesis, a new method based on the Average Position (AP) is used to estimate the position of the positive edges. The AP method is compared with other techniques with similar complexity as the FE, Last Edge (LE) or ZC methods.

A brief description of the compared debouncing methods is given below.

• First Edge estimates the positive edge time position as the first positive edge detected.

• Last Edge estimates the positive edge time position as the last positive edge detected.

• Zero Count counts the number of ones and zeros produced during the glitch period and estimates the positive edge position where the number of zeros and ones are equal.

• Average Position calculates the positive edge time position as the average value between the time position provided by the First Edge and Last Edge methods.

Figure 5.11 presents a timing diagram of the debouncing operation with AP method. The AP method estimates the positive edge using the values obtained with the FE and LE methods. The FExand LExpulses are generated to detect the first and the last positive glitches of the Ux signals. Then, the estimated positive edge of the U1 (tstart) and U2 (tstop) is obtained by calculating the average time between the arrival time of the corresponding FE and LE pulses.

t0 t1

t2 t3

U1

U2

F E1

LE1

F E2

LE2

tstop

tstart

Figure 5.11: Timing diagram of the AP debouncing method describing the process to estimate the positive edge position of the U1 and U2 signals.

As expressed in Equation 5.23, the estimated phase difference between the U_x corresponds to the time difference between the t_start and t_stopsignals.

∆t = tstop− tstart=(t3+ t2)

2 −(t1+ t0)

2 (5.23)

Finally, Equation 5.23 can be rewritten as presented in Equation 5.24 to facilitate the implementation of the algorithm in the FPGA.

∆t =(t2− t0)

2 +(t3− t1)

2 (5.24)

Thereby, the AP method is implemented in the FPGA with two time coun-ters, where the number of clock cycles between the F E_x and LE_x signals are counted separately and then subtracted.

Debouncing techniques comparison

The four debouncing techniques were tested to compare the resolution of the AP method. An OSUS circuit was implemented in the Readout FPGA con-taining four different sets of debouncer blocks. The result of the comparison is presented in Figure 5.12, where each histogram contains 500,000 measurements corresponding to the phase difference between a pair of 240 MHz clocks. The OSUS circuit was implemented with a factor M equal to 1 and the PLL was configured a factor N equal to 16384.

Phase difference (ns)

−1.8 −1.75 −1.7 −1.65 −1.6 −1.55 −1.5

Counts

0 50 100 150 200 250

103

×

Average Position Zeroes First Edge Last Edge

Figure 5.12: Comparison of the four debouncing methods measuring two 240 MHz clocks. The OSUS circuit was configured with M = 1 and the PLL with N = 16384.

Table 5.1 shows the time resolution corresponding to the four methods com-pared in Figure 5.12.

Debouncing technique Resolution_RMS

Average Position 29.12 ps

Zero Count 29.5 ps

First Edge 44.66 ps

Last Edge 44.57 ps

Table 5.1: Time resolution obtained with the AP, ZC, FE and LE methods.

As can be concluded from Figure 5.12 and Table 5.1, the AP and ZC methods provide a much better resolution than the FE and LE techniques, with an improvement of about 15 ps_RMS. Although the number of logic resources needed to implement the AP and ZC algorithms are very similar, the AP shows a slightly better time resolution than the ZC method. For this reason, the AP method was used in the TilePPr prototype to debounce the output signals coming from the OSUS samplers.