3.7 Conclusions
4.1.2 PICDiY’s Instructions
The RISC architecture of the PICDiY, allows higher CPU operating frequencies and implies that it has a reduced number of instructions, which means simplicity in programming, since it is necessary to manage just a small number of instruc-tions. As Table 4.1 shows, the processor uses 33 instructions of a 14 bit width, divided into byte-oriented file register operations (18 instructions), bit-oriented file register operations (4 instructions) and literal and control operations (11 in-structions). It has to be remarked that, due to the removal of the timers, PIC16’s SLEEP and CLRWDT instructions are not available. Each instruction takes a sin-gle machine cycle consisting of four clock periods for the execution, that is an improvement over the PIC16, since it uses two machine cycles for instructions which modify the value of the program counter. All of the instruction are stored in the program memory.
Figure 4.7 shows the general instruction format for byte-oriented file register operations. As it can be observed, the highest five bits are mainly used to define the opcode, the 7th bit is used to set the direction of result’s value (d) for the ALU and the lowest 7 bits are the file registers address.
Figure 4.7: Byte-oriented file register operations instruction format.
Figure 4.8 shows bit-oriented file register operations instruction format. The
Instruction Description Instruction Code Flags STATUS Byte-Oriented File Register Operation
ADDWF f, d f + W 00 0111 dfff ffff C, DC, Z
ANDWF f, d f AND W 00 0101 dfff ffff Z
CLRF f Clear f 00 0001 1fff ffff Z
CLRW - Clear W 00 0001 0fff ffff Z
COMF f, d Complement f 00 1001 dfff ffff Z
DECF f, d Decrement f 00 0011 dfff ffff Z
DECFSZ f, d Decrement f, skip if 0 00 1011 dfff ffff
-INCF f, d Increment f 00 1010 dfff ffff Z
INCFSZ f, d Increment f, skip if 0 00 1111 dfff ffff
-IORWF f, d f OR W 00 0100 dfff ffff Z
MOVF f, d Move f 00 1000 dfff ffff Z
MOVWF f Move W to f 00 0000 1fff ffff
-NOP - No operation 00 0000 0xx0 0000
-RLF f, d Rotate left f through carry 00 1101 dfff ffff C RRF f, d Rotate right f through carry 00 1100 dfff ffff C
SUBWF f, d f - W 00 0010 dfff ffff C, DC, Z
SWAPF f, d Swap nibbles in f 00 1110 dfff ffff
-XORWF f, d f OR W 00 0110 dfff ffff Z
Bit-Oriented File Register Operation
BCF f, b Bit clear f 01 00bb bfff ffff
-BSF f, b Bit set f 01 01bb bfff ffff
-BTFSC f, b Bit test, skip if clear 01 10bb bfff ffff -BTFSS f, b Bit test, skip if set 01 11bb bfff ffff -Control and Literal Operations
ADDLW k Literal + W 11 111x kkkk kkkk C, DC, Z
ANDLW k Literal AND W 11 1001 kkkk kkkk Z
CALL k Call a subroutine 10 0kkk kkkk kkkk
-GOTO k Go to k address 10 1kkk kkkk kkkk
-IORLW k Literal OR W 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 11 00xx kkkk kkkk -RETFIE - Return from interrupt 00 0000 0000 1001 -RETLW k Return with literal in W 11 01xx kkkk kkkk -RETURN - Return from subroutine 00 0000 0000 1000
-SUBLW k Literal - W 11 110x kkkk kkkk C, DC, Z
XORLW k Literal XOR W 11 1010 kkkk kkkk Z
Table 4.1: Instruction set of the PICDiY.
highest four bits are used to define the opcode, the next three bits are used to specify which bit will be written and the lowest 7 bits are the file registers address.
Figure 4.8: Bit-oriented file register operations instruction format.
Figure 4.9 shows the general instruction format for literal operations, where the highest six bits are generally used to define the opcode and the other 8 bits are the literal value.
Figure 4.9: Literal operations instruction format.
In the case of GOTO and CALL control instruction, which are depicted in Figure 4.10, the highest three bits define the opcode and the other bits are used to set the destination address.
Figure 4.10: Control operations instruction format.
In order to store the actual instruction address when CALL instruction or an interrupt are executed, the program counter is connected with the 8-level stack, where the processor can store up to 8 addresses. It has to be noticed that the depth of the stack limits the number of CALL instructions to be used, since it can lead to a stack overflow. Nevertheless, the depth of the stack can easily be changed according to the application needs.
The interrupt system works level triggered and due to this, the interrupt signal must have certain specifications. First, the interrupt signal is active high and since the interrupt attention is done in one of the four states of the FSM, it is necessary that the interrupt signal remains stable at least four clock cycles to ensure that the interrupt signal is detected. There is also a maximum duration for the interrupt signal, as long as a signal that lasts for a long time, can call the interruption routine more than a single time. This maximum duration depends on the number of executed instructions in the interruption routine. In the worst
case, after the execution of the RETURN FROM INTERRUPT instruction the interrupt signal must be in low level. When, in order to respond to external events, the interrupt input is set to high level and the interrupt conditions are fulfilled, the program counter changes the program flow jumping to the fourth address of the program memory to execute the interrupt routine, after this execution it continues from the previous point on.
As the presented features imply, thanks to the basic and modular architecture of 8-bits, an easily adaptable, self-sufficient and platform-independent soft-core processor has been designed.