Chapter 5 – BIOS User Interface
Chapter 6 – Connector/Header Locations and Pin-outs
Chapter 7 – Jumpers Blocks
Chapter 8 – Intel® Light-Guided Diagnostics
Chapter 9 – Design and Environmental Specifications
Chapter 10 – Regulatory and Certification Information
Chapter 11 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – Integrated BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel® Server Chassis
Glossary
Reference Documents
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system meets the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.
2. Overview
The Intel® Server Board S3420GP is a monolithic printed circuit board (PCB) with features designed to support entry-level severs. It has three board SKUs: S3420GPLX, S3420GPLC, and S3420GPV.
2.1 Intel
®Server Board S3420GP Feature Set
Table 1. Intel® Server Board S3420GP Feature Set
Feature Description
Processor Support for one Xeon® Processor 3400 Series or Intel® CoreTM Processor i3-500 Series or Intel® Pentium® Processor G6950 in FC-LGA 1156 socket package.
2.5 GT/s point-to-point DMI interface to PCH
LGA 1156 pin socket
Memory Two memory channels with support for 1066/1333 MHz ECC Unbuffered (UDIMM) or ECC Registered (RDIMM) (Intel® Xeon® Processor 3400 Series only) DDR3.
Intel® Server Board S3420GPLX and S3420GPLC
Up to 2 UDIMMs or 3 RDIMM (Intel® Xeon® Processor 3400 Series only) per channel
32 GB max with x8 ECC RDIMM (2 Gb DRAM) and 16 GB max with x8 ECC UDIMM (2 Gb DRAM)
Intel® Server Board S3420GPV
Up to 2 UDIMMs or 2 RDIMM (Intel® Xeon® Processor 3400 Series only) per channel
16 GB max with x8 ECC UDIMM (2 Gb DRAM) and 16 GB max with x8 ECC RDIMM (2 Gb DRAM)
Chipset Intel® Server board S3420GPLX
Support for Intel® 3420 Chipset Platform Controller Hub (PCH)
ServerEngines* LLC Pilot II BMC controller (Integrated BMC)
PCI Express* switch Intel® Server board S3420GPLC
Support for Intel® 3420 Chipset Platform Controller Hub (PCH)
ServerEngines* LLC Pilot II BMC controller (Integrated BMC) Intel® Server board S3420GPV
Support for Intel® 3420 Chipset Platform Controller Hub (PCH) I/O External connections:
DB-15 video connectors
DB-9 serial Port A connector
Four ports on two USB/LAN combo connectors at rear of board.
Internal connections:
Two USB 2x5 pin headers, each supporting two USB 2.0 ports (Only one header for Intel® Server board S3420GPV)
One 2x5 Serial Port B header (Intel® Server board S3420GPLX and S3420GPLC)
Six SATA II connectors
One connector supports for optional Intel® Remote Management Module 3 (Intel® Server board S3420GPLX)
Revision 2.4
Intel order number E65697-010 3
Feature Description
Add-in PCI Card, PCI
Express* Card Intel® Server Board S3420GPLX
Slot1: One 3.3V/5V PCI 32 bit/33 MHz connector.
Slot2: One PCI Express* Gen1 x4 (x1 throughput) connector.
Slot3: One PCI Express* Gen1 x8 (x4 throughput) connector.
Slot4: One PCI Express* Gen2 x8 (x4 throughput) connector.
Slot5: One PCI Express* Gen2 x8 (x8 throughput) connector.
Slot6: One PCI Express* Gen2 x16 (x8 throughput) connector.
Intel® Server Board S3420GPLC/ S3420GPV
Slot1: One 3.3V/5V PCI 32 bit/33 MHz connector.
Slot3: One PCI Express* Gen1 x8 (x4 throughput) connector.
Slot5: One PCI Express* Gen2 x8 (x8 throughput) connector.
Slot6: One PCI Express* Gen2 x16 (x8 throughput) connector.
System Fan Support Five 4-pin fan headers supporting four system fans and one processor.
Video Intel® Server Board S3420GPLX/ S3420GPLC
Onboard ServerEngines* LLC Pilot II BMC Controller
Integrated 2D Video Controller with 8MB Video Memory
64-MB DDR2 667 MHz Memory Intel® Server Board S3420GPV
Silicon Motion SM712GX04LF02-BA
Onboard Hard Drive Support for six Serial ATA II hard drives through six onboard SATA II connectors with SW RAID 0, 1, 5, and 10.
Intel® Server Board S3420GPLX:
Up to four SAS hard drives through option Intel® SAS Entry RAID Module card
RAID Support Intel® Server Board S3420GPLX /S3420GPLC/S3420GPV
Intel® Rapid Storage RAID through onboard SATA connectors provides SATA RAID 0, 1, 5 and 10.
Intel® Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0, 1, and 10.
Intel® Server Board S3420GPLX
Intel® Embedded Server RAID Technology II through optional Intel® SAS Entry RAID Module AXX4SASMOD provides SAS RAID 0, 1, and 10 with optional RAID 5 support provided by the Intel® RAID Activation Key AXXRAKSW5
IT/IR RAID through optional Intel® SAS Entry RAID Module AXX4SASMOD provides entry level hardware RAID 0, 1, 10, and native SAS pass through mode
Four ports full featured SAS/SATA hardware RAID through optional Intel® Integrated RAID Module SROMBSASMR (AXXROMBSASMR) provides RAID 0, 1, 5, 6 and striping capability for spans 10, 50, 60.
LAN One Gigabit Ethernet device 82574L connect to PCI-E x1 interfaces on the PCH.
One Gigabit Ethernet PHY 82578DM connected to PCH through PCI-E x1 interface.
Feature Description Server Management Intel® Server Board S3420GPLX/S3420GPLC:
Onboard LLC Pilot II Controller (iBMC)
Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant
Integrated 2D video controller on PCI-E x1 Intel® Server Board S3420GPLX
Intel® Remote Management Module III (RMM3)
Revision 2.4
Intel order number E65697-010 5
2.2 Server Board Layout
Figure 1. Intel® Server Board S3420GPLX Picture
2.2.1 Server Board Connector and Component Layout
The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and Table 2 provides the description.
AF003290 CC
DD
A B C D E F G H I J K
L M
N
O
P
Q R
S T
U WV
X Y Z AA
BB
Figure 2. Intel® Server Board S3420GP Layout
Revision 2.4
Intel order number E65697-010 7 Table 2. Major Board Components
Description Description
A Slot 1, 32 Mbit/33 MHz PCI Q System FAN2 and System FAN 3 B Slot 2, PCI Express* Gen1 x1 (x4 connector)
(Intel Server Board S3420GPLX only) R CPU connector C Intel RMM3 Connector(Intel Server Board
S3420GPLX only) S CPU Fan connector
D Slot 3, PCI Express* Gen1 x4 (PCI Express*
Gen2 compliant) T USB SSD connector (Intel® Server Board S3420GPLX and S3420GPLC)
E Slot 4, PCI Express* Gen2 x4 (x8 connector) (x8 connector)( Intel® Server Board S3420GPLX only)
U 50-pin PCI Express* connector (Intel® Server Board S3420GPLX only)
F Slot 5. PCI Express* Gen2 x8 (x8 connector) V System FAN 1 (Intel® Server Board S3420GPLX and S3420GPLC)
G Slot 6, PCI Express* Gen2 x8 (x16 connector) W IPMB(Intel® Server Board S3420GPLX and S3420GPLC)
H CMOS battery X SATA_SGPIO
I Ethernet and Dual USB COMBO Y HSBP (Intel® Server Board S3420GPLX and S3420GPLC)
J Ethernet and Dual USB COMBO Z USB Floppy (Intel® Server Board S3420GPLX and S3420GPLC)
K System FAN 4 AA Six SATA ports
L Video port BB Internal USB Connector ( One for Internal USB header on Intel® Server Board S3420GPV) M External Serial port CC Front Panel Connector
N Main Power Connector DD Internal Serial Port (Intel® Server Board S3420GPLX and S3420GPLC)
O CPU Power connector
P DIMM slots (4 slots on Intel® Server Board S3420GPV)
2.2.2 Intel® Server Board S3420GP Mechanical Drawings
Figure 3. Intel® Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION
Revision 2.4
Intel order number E65697-010 9 Figure 4. Intel® Server Board S3420GP – Hole and Component Positions
Figure 5. Intel® Server Board S3420GP – Major Connector Pin Location (1 of 2)
Revision 2.4
Intel order number E65697-010 11 Figure 6. Intel® Server Board S3420GP –Major Connector Pin Location (2 of 2)
Figure 7. Intel® Server Board S3420GP – Primary Side Keepout Zone
Revision 2.4
Intel order number E65697-010 13 Figure 8. Intel® Server Board S3420GP – Secondary Side Keepout Zone
2.2.3 Server Board Rear I/O Layout
The following figure shows the layout of the rear I/O components for the server board.
A Serial Port A C NIC Port 1 (1 Gb) and Dual USB Port Connector
B Video D NIC port 2 (1 Gb) and Dual USB Port Connector
Figure 9. Intel® Server Board S3420GP Rear I/O Layout
Revision 2.4
Intel order number E65697-010 15
3. Functional Architecture
The architecture and design of the Intel® Server Board S3420GP is based on the Intel®3420 Chipset. The chipset is designed for systems based on the Intel® Xeon® Processor 3400 Series or Intel® CoreTM i3-500 Desktop Processor Series or Intel® Pentium® Processor Processor G6950in the FC-LGA 1156 socket package. The chipset contains two main components:
Intel® 3420 Chipset
PCI Express* switch (Intel® Server Board S3420GPLX only).
This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server board.
Figure 10. Intel® Server Board S3420GP Functional Block Diagram For S3420GPLX
Figure 11. Intel® Server Board S3420GP Functional Block Diagram From S3420GPLC
Revision 2.4
Intel order number E65697-010 17 Figure 12. Intel® Server Board S3420GP Functional Block Diagram From S3420GPV
3.1 Processor Sub-System
The Intel® Server Board S3420GP supports the following processor:
Intel® Xeon® Processor 3400 series
Intel® CoreTM Processor i3-500 Desktop series
Intel® Pentium® Processor G6950
The Intel® Xeon® 3400 Processor Series are made up of multi-core processors based on the 45 nm processor technology. The Intel® CoreTM Processor i3-500 Series and Intel® Pentium®
Processor G6950are made up of dual core processor based on the 32 nm processor technology.
3.1.1 Intel® Xeon® Processor 3400 Series
The Intel® Xeon® Processor 3400 Series highly integrated solution variant is composed of four Nehalem-based processor cores.
FC-LGA 1156 socket package with 2.5 GT/s.
Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not supported.
The server board does not support previous generations of the Intel® Xeon® processors.
3.1.2 Intel® CoreTM Processor i3-500 Series and Intel® Pentium® Processor G6950 The Intel® Duo CoreTM Processor i3-500 Series and Intel® Pentium® Processor G6950 highly integrated solution variant is composed of two processor cores.
FC-LGA 1156 socket package with 2.5 GT/s.
Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not supported.
Please get the detail supported processor list from Intel website.
3.1.3 Intel® Turbo Boost Technology
Intel® Turbo Boost Technology is featured on certain processors in the Intel® Xeon® Processor 3400 Series. Intel® Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the processor is operating below power, temperature, and current limits. This results in increased performance for both multi-threaded and single-threaded workloads.
Intel® Turbo Boost Technology operation:
Turbo Boost operates under Operating System control – It is only entered when the operating system requests the highest (P0) performance state.
Turbo Boost operation can be enabled or disabled by BIOS.
Turbo Boost converts any available power and thermal headroom into higher frequency on active cores. At nominal marked processor frequency, many applications consume less than the rated processor power draw.
Turbo Boost availability is independent of the number of active cores.
Maximum Turbo Boost frequency depends on the number of active cores and varies by processor configuration.
The amount of time the system spends in Turbo Boost operation depends on workload, operating environment, and platform design.
If the processor supports the Intel® Turbo Boost Technology feature, the BIOS Setup provides an option to enable or disable this feature. The default state is enabled.
3.1.4 Simultaneous Multithreading (SMT)
Most Intel® Xeon® processors support Simultaneous Multithreading (SMT). The BIOS detects processors that support this feature and enables the feature during POST.
If the processor supports this feature, the BIOS Setup provides an option to enable or disable this feature. The default is enabled.
3.1.5 Enhanced Intel SpeedStep® Technology
Most processors support the Enhanced Intel SpeedStep® technology. This technology changes the processor operating ratio and voltage similar to the Thermal Monitor 1 (TM1) feature. The BIOS implements this technology in conjunction with the TM1 feature.The BIOS enables a combination of TM1 and TM2 according to the processor BIOS writer's guide.
3.2 Memory Subsystem
The Intel® Xeon® Processor 3400 Series has an Integrated Memory Controller (IMC) in its package. Each Intel® Xeon® Processor 3400 Series produces up to two DDR3 channels of memory. Each DDR3 channel in the IMC supports up to three DDR3 RDIMM slots or up to two UDIMM slots. The DDR3 RDIMM frequency can be 800/1066/1333 MHz. DDR3 UDIMM frequency can be 1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction Code) operation. Various speeds and memory technologies are supported.
Note: Intel® Xeon® Processor L3406 only supports DDR3 Unbuffered DIMM (UDIMM).
The Intel® CoreTM Processor i3-500 Series and Intel® Pentium® Processor G6950 have an Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. Only DDR3 UDIMM can be supported with the Intel® Core® i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950.
RAS (Reliability, Availability, and Serviceability) is not supported on the Intel® Server Board S3420GP.
3.2.1 Memory Sizing and Configuration
The Intel® Server Board S3420GP supports various memory module sizes and configurations.
These combinations of sizes and configurations are valid only for DDR3 DIMMs approved by Intel Corporation.
Revision 2.4
Intel order number E65697-010 19 S3420GP supports:
DIMM sizes of 1 GB, 2 GB, 4 GB, and 8 GB.
DIMMs composed of DRAM using 2 Gb technology.
DRAMs organized as single rank, dual rank, or quad rank DIMMS.
DIMM speeds of 800, 1066, or 1333 MT/s.
Registered or Unregistered (unbuffered) DIMMs (RDIMMs or UDIMMs).
Note: UDIMMs should be ECC, and may or may not have thermal sensors; RDIMMs must have ECC and must have thermal sensors.
S3420GP has the following limitations:
256 Mb technology, x4 DRAM on UDIMM, and quad rank UDIMM are NOT supported
x16 DRAM on UDIMM is not supported on combo routing
Memory suppliers not productizing native 800 ECC UDIMMs
Intel® Xeon® 3400 Series support all timings defined by JEDEC.
256 Mb/512 Mb technology, x4 and x16 DRAMs on RDIMM are NOT supported
All channels in a system will run at the fastest common frequency
No mixing of registered and unbuffered DIMMs
No mixing of different ranks or speeds on UDIMM or RDIMM.
3.2.2 Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, this range is used for reporting other system errors.
0xE8 - No Usable Memory Error: If no memory is available, the system emits POST Diagnostic LED code 0xE8 and halts the system.
0xE8 - Configuration Error: If a DDR3 DIMM has no SPD information, the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only DDR3 DIMM installed in the system, the BIOS halts with POST Diagnostic LED code 0xE8 (no usable memory) and halts the system.
0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the same memory channel (row) fails HW Memory BIST but usable memory remains available, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily during the beeping and then continues POST. If all of the memory fails HW Memory BIST, the system acts as if no memory is available, beeping and halting with the POST Diagnostic LED code 0xE8 (No Usable Memory) displayed.
0xEA - Channel Training Error: If the memory initialization process is unable to properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping. If there is usable memory in the system on other channels, POST memory initialization continues. Otherwise, the system halts with POST Diagnostic LED code 0xEA staying displayed.
0xED - Population Error: If the installed memory contains a mix of RDIMMs and UDIMMs, the system halts with POST Diagnostic LED code 0xED.
0xEE - Mismatch Error: If more than two quad-ranked DIMMs are installed on any channel in the system, the system halts with POST Diagnostic LED code 0xEE.
3.2.3 Publishing System Memory
The BIOS displays the Total Memory of the system during POST if Quiet Boot is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.
The BIOS displays the Effective Memory of the system in the BIOS Setup. The term Effective Memory refers to the total size of all active DDR3 DIMMs (not disabled) and not used as redundant units.
The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet in this section.
If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet in this section.
The BIOS provides the total amount of memory in the system.
3.2.3.1 Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
processor, and BIOS (flash) spaces as memory-mapped I/O regions. This region appears as a loss of memory to the operating system. In addition to this loss, the BIOS creates another reserved region for memory-mapped PCIe functions, including a standard 64 MB or 256 MB of standard PCI Express* MMIO configuration space.
If PAE is turned on in the operating system, the operating system reclaims all these reserved regions.
In addition to this memory reservation, the BIOS creates another reserved region for memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of standard PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the selection of Maximize Memory below 4 GB in the BIOS Setup.
If this is set to Enabled, the BIOS maximizes usage of memory below 4 GB for an operating system without PAE capability by limiting PCI Express* Extended Configuration Space to 64 buses rather than the standard 256 buses. This is done using the MAX_BUS_NUMBER feature offered by the Intel® S3420 I/O Hub and a variably-sized Memory Mapped I/O region for the PCI Express* functions.
3.2.3.2 High-Memory Reclaim
When 4 GB or more of physical memory is installed (physical memory is the memory installed as DDR3 DIMMs), the reserved memory is lost. However, the Intel® 3420 chipset provides a feature called high-memory reclaim, which allows the BIOS and operating system to remap the lost physical memory into system memory above 4 GB (the system memory is the memory the processor can see).
The BIOS always enables high-memory reclaim if it discovers installed physical memory equal to or greater than 4 GB. For the operating system, the reclaimed memory is recoverable only if the PAE feature in the processor is supported and enabled. Most operating systems support this feature. For details, see the relevant operating system manuals.
Revision 2.4
Intel order number E65697-010 21
3.2.3.3 ECC Support
Only ECC memory is supported on this platform.
3.2.4 Memory Map and Population Rules
The following nomenclature is followed for DIMM sockets:
Note: Intel® Server Board S3420GP may support up to three DIMM sockets per channel.
Table 3. Standard Platform DIMM Nomenclature
Channel A Channel B
A1 A2 A3 B1 B2 B3
3.2.4.1 TableMemory Subsystem Operating Frequency Determination
The rules for determining the operating frequency of the memory channels are simple, but not necessarily straightforward. There are several limiting factors, including the number of DIMMs on a channel and organization of the DIMM - that is, either single-rank (SR), dual-rank (DR), or quad-rank (QR):
The speed of the processor’s IMC is the maximum speed possible.
The speed of the slowest component – the slowest DIMM or the IMC – determines the maximum frequency, subject to further limitations.
A single 1333-MHz DIMM (SR or DR) on a channel may run at full 1333-MHz speed.
If two SR/DR DIMMs are installed on a channel, the speed is limited to 1066 MHZ.
A single QR RDIMM on a channel is limited to 1066 MHz.
Two QR RDIMMs or a mix of QR + SR/DR on a channel is limited to 800 MHz.
3.2.4.2 Memory Subsystem Nomenclature
1. DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets.
2. The memory channels are identified as channels A, B.
2. The memory channels are identified as channels A, B.