PLC SYSTEMS I MPLEMENTATION

The PLC implementation set up is based on the block diagram shown in Fig. 7.1. It in-cludes six main sub-blocks including the data source, the modulator, two coupling circuit (transmitter and receiver), the demodulator and the data recipient. Their description is given as follows:

• The data source

A computer and a signal generator are available to be used as data sources. The computer will produce random ”1s” and ”0s” while the signal generator will produce a square wave seen as a signal representing ”1s” and ”0s”. The difference lies on the fact that with the computer, it is possible to generate real random number as in the real word. A 232 protocol is needed in this case to convert that real variable random data into an electric signal which will be used for modulation, while with the signal generator the needed signal is obtained at its output.

Figure 7.1:Schematic of final PLC design.

• Modulator

This block maps signals representing each frequency to the assigned symbol depending on the modulation level used. In the case of SFSK, the two symbols transmitted will be done so while ensuring that the differences between them is at least 10 kHz. The mono-lithic function generator XR2206 integrated circuit was exploited to serve as modulator in which the two carrier frequencies here are determined based on the relations f1= _R¹

1C

and f2= _R¹

2C., based on the integrated circuit data sheet. the XR2206 is a monolithic func-tion generator capable of producing waveforms such as ramp, sine, triangular and square waves with high stability. It is also a native FSK circuit with operation frequencies vary-ing from 0.01 Hz to over 1 MHz, where the latest is the maximum frequency that the IC can produce with less distortion. In order to get the FSK signal, the timing resistors R1

and R2are connected to the timing Pins 7 and 8 respectively. The resistors activation are dependent on the polarity of the logic signal entering pin 9. For a bias voltage ≥ _{2V at} pin 9, R₁is activated, a similar situation is observed when pin 9 is open circuit. When the voltage at pin 9 is ≤1 V, this activates R2. The net effect is the keying of the output fre-quencies f₁and f2. For the layout of the circuit used in this implementation, please refer

to the appendix. A current amplifier (see Fig. 7.1) steps up the current from the XR2206 in order to challenge the low impedance of the channel. The amplifier is built using the NPN transistor 2N2219. The output power produced by the transistor is around 2.5 W.

This power is enough to achieve a normal PLC transmission in narrow-band for a short distance.

• Coupling Circuit

The coupling circuit was designed to allow only the carrier frequencies to go through the Modem. Hence, it filters out frequencies in the range of 0-30000 Hz which is approxi-mately equal to fc(the cut-off frequency) the range at which the rated 220 V mains supply operates. The coupling circuit is seen as a filter capable of selecting needed frequencies and blocking unwanted ones. Following this ideology, it clears any signal with frequency between 0 - 1000 Hz in the forward direction thus allowing the transmitted data to freely travel via the mains. At reception, a similar filter is used after which the remaining signal simply represents the modulated data. Next, demodulation is done after which the data is converted back to bits. The block representing the coupling circuit is given in Fig. 7.2 (a). It shows that part of the the frequencies coming from the modem to the main are filtered out and low frequencies from the channel are blocked. This is a double role as the coupling circuit also protects the modem and other circuits against the 220V. Fig.7.2 (b) is the transfer function of a coupling circuit indicating the transmission bandwidth (within which the accepted frequencies are located), which in our case lies between 30000 Hz and 140 kHz. The principle circuit diagram of a coupling circuit is depicted in Fig.7.3.

It is a bandpass filter whose cut off frequency discards the 220V 50Hz signal and all other signals lying in the frequency band from 0 to 30000 Hz, in favour of frequencies between 30000 Hz and 140 kHz, including the carrier frequencies. Basically, the built coupling cir-cuit is made of a high voltage capacitor, a 1:1 high frequency low impedance transformer, and two Zener diodes mounted in opposition. One winding of the transformer in series with the high voltage capacitor (0.1 µF, 0.22 µFand0.24µF were used) form a voltage di-vider and connected to the mail. In general, the capacitor must be able to handle more than 220V. Practically, 400V capacitors are used. Exploiting the voltage division principle

Figure 7.2:Mode of Operation of the coupling circuit.

Figure 7.3: Circuit diagram of Coupling circuit.

makes sure that at most very little voltage is applied to the first winding of the trans-former. The second winding of the transformer connected in parallel with the two Zener diodes in opposition forms the modem side of the coupling circuit. All signals that the voltage is greater than 6.2V, 5.5V (Zener) + 0.7 (normal diode) = 6.2 V, is automatically cut off by the two Zener diodes to protect all equipment connected modem side. Note that both transmitter and receiver modems are similar. The only difference is related to direc-tion of the transmitted signal which is modem to channel for the first one and channel to modem for the second.

• Channel

The power line channel is made of wires exploited to transmit electrical energy from one point to another. In general, the indoor environment of PLC is made on 2 wires (phase and neutral), 3 wires (phase, neutral and protection wire), 4 wires (three phases and the neutral) etc. It also includes all equipment attached to the electrical network. In indoor, all appliances connected to the network participate to the building of the power

line impedance, which in general, is very low (between 0.1Ω and 2 Ω) as result of parallel connection of the appliances. This channel is a frequency selective channel as presented in [41]. This motivated the work which led to defining the PLC channel as two different part including the narrowband part made of frequencies between 0 and 500 kHz and the broadband part made of other frequencies up to 300 MHz. In this work, we are interested in the narrowband part. This even motivated the characterisation of our coupling circuit with a bandwidth between 30000 Hz and 140 kHz. This frequency band includes our communication frequencies which are between 80 kHz and 100 kHz.

• Demodulation

The role of this block is to de-map the transmitted signal into symbols based on their re-spective frequencies. it converts back to data the analogue received signal. The XR2211 was exploited as demodulator in our case. The RX-2211 FSK Demodulator/Tone Decoder This is a data communication chip suitable for FSK based modems. It works best in the voltage range of 4.5V - 20V and its frequency range spans from 0.01 Hz to 300 kHz hence making this suitable for this investigation. The block diagram of this chip and the lay-out used in this implementation can be found in the appendix. In order for this chip to decode FSK signals, the resistor RD and the capacitor CD which are set to the PLL centre Frequency. The resistor R1 sets the bandwidth of the entire system while the capacitor C1sets the loop damping factor and filter time constant. Next, we have the capacitor CT

and resistor RT which are used for pole post detection filtering of the FSK output signal.

Positive feedback across the FSK comparator is achieved by connecting a resistor RBfrom pin 7 to 8.

where: R1 and R2 are the timing resistors and C the timing capacitor. As such, the output frequency will be keyed between two levels f1 and f2 The transmission is char-acterised by the parameters listed below. (the formulas are extracted from [12]). The tracking system and the frequency classification are illustrated in Fig. 4.4.

• Phase locked loop detection;

• Narrow-band communication (Bandwidth≤25 kHz);

Figure 7.4:FSK tracking bandwidth.

• Non-coherent detection;

• Frequencies [kHz]: f1=_{100, f2}=₁₂₅

• Centre frequency [Hz]: f0=111803.4

• Bandwidth: ^{∆ f}_f

The main components and their technical details are as detailed in the appendix as well as the description of each pin.

In summary, Fig.7.1 presented earlier is a generalized communication system based on these two components for modulation and demodulation of the transmitted signal.

Figure 7.5: Communication System

(a)Transmission system. (b)Modulator coupled to power line.

Figure 7.6:Transmitting unit.

7.1.1 P

PLC

The entire physical system following the design is as shown on Fig.7.5. This was im-plemented following the general frame work of a communications system. The signals source finally used in the implementation was a signal generator with which bits were sent by applying square waves. As such, each bit represented a symbol since we were limited to 2FSK as presented in th design. The generated message was sent to the XR-2206 modulator which was designed to attribute a frequency of f1 to 1s and f2 to 0s. The ana-logue signal generated was coupled to the power line. The transmitting unit based on the XR-2206 modulator chip is shown on Fig.7.6. The transmission system which generates and sends the signals on the power line is presented in Fig.7.6-a while Fig.7.6-b gives a view of the connection between the modulator and the coupling circuit.

Likewise, the receiving unit is shown on Fig.7.7. This was designed to be in sync with the modulating unit. The received signal was displayed on a computer in character form. The characters were then reconverted to bits hence BER computation could easily be done. Fig.7.7-a shows the receiving system and Fig.7.7-b is the connection between the coupling circuit and the demodulator which together helps retrieve the signal from the

(a)Receiving system. (b)Modulator coupled to power line.

Figure 7.7: Receiving unit.

(a)Sender and coupling circuit. (b)Receiver and coupling circuit.

Figure 7.8:Modulator and demodulator circuits.

power line.

Channel:

As stated, we are dealing here with the power line and the mains supply voltage was 220V. This had to be taken care of by properly coupling the signals during transmission at both ends (transmission and reception). Hence coupling circuits had to come into play to guarantee safety during transmission. Fig.7.8 (a and b) shows the coupling circuits used at both entery and exit points of the power line.

7.1.2 PLC R

In the PLC implementation, the scope of this research was narrowed down to 2FSK and S-FSK where the modulating frequencies were 80 kHz and 84.6 kHZ (for 2FSK), 80 kHz and 109.8 kHz (for S-FSK). Fig.7.9 is a view of the S-FSK signal and we can appreciate the digital signal and the FSK modulation done based on the two symbols transmitted (”1”

and ”0”).

Figure 7.9: FSK signal generated.

(a)Signal in channel. (b)Noise spectrum in power line.

Figure 7.10:Spectra Of signal in channel and channel noise.

Using the fast fourier transform (FFT), the nature of the signal transmitted and the noise spectrum in the power line could be visualized. Fig.7.10-a shows the spectrum of the two signals with the associated harmonics while Fig.7.10-b indicates high noise amplitude from 0-30 kHz and the narrow band as well which is better for transmission in this case.

Contrary to what was done in simulation, variation of the signal to noise ratio over the power line in real time applications is not easy as per say. Hence it made it difficult to come up with a BER vs SNR curve. However, to make sense out of the investigation performed, 10 ”TEST” transmissions were done using each scheme (2FSK and S-FSK) and

Table 7.1: Implementation results

the respective BER were computed as well. The average of the BER were taken and the results obtained are as shown in table 7.1.

The results obtained are conclusive that on average, S-FSK performs better than 2FSK.

This was done at random intervals in order to have convincing evidence of the outcome before drawing conclusions on the performance of each scheme over the power line chan-nel. Also, for each test case, there was no instance whereby 2FSK outperformed S-FSK and in all there is an average difference of 0.05105 in their BER. This alone is quite significant as in communication, a single bit reversal/change can be very significant depending on the application for which it is intended.

Comparing these results with analytical results, it is clear that the noise experienced in real time applications is more sever than what is used in analysis (AWGN+impulsive) to simulate the PLC channel. This is due to the fact that the PLC channel presents other noise types such as narrow band noise which results in much signal degradation. It is also worthy noticing that the probability of occurrence of the impulsive noise used in the analysis does not follow the same pattern as what happened practically. However, the point of interest remains that during these tests S-FSK performed better than 2FSK.