Power Consumption Performance

Table 5.6 shows the power consumption for the sub blocks of the designed ADC Table 5.6: Power consumption performance.

Power of comparator 4.68mW

Power of DAC 4.94mW

Power of SAR logic 1.38mW

Total Power of ADC 11mW

Total power consumption is 11𝑚𝑊 for the whole ADC as shown in the previous table. With the calculated power consumption, the Table 5.7 is created for comparison the differences between some TI-SAR ADCs.

60

Table 5.7: Comparison for some TI-SAR ADCs.

Talekar et al. (2009) Akita et al. (2011) Kundu et al. (2014) Fang et al. (2015) This Thesis Technology 180 nm 65 nm 40 nm 28 nm 180 nm

Resolution 4-bit 7-bit 8-bit 10-bit 8-bit

Speed 700 MS/s 1.5 GS/s 2.64 GS/s 5 GS/s 2 GS/p Power

Consumption 23.3 mW 36 mW 39 mW 76 mW 11 mW

In the (Lee, Chandrakasan, & Lee, 2014) ±1𝐿𝑆𝐵 INL/DNL levels are achieved at 1𝐺𝑆𝑃𝑆 and SINAD is achieved 39.6𝑑𝐵 in the (Akita, Furuta, Matsuno, & Itakura, 2011). The (Kundu, et al., 2014) achieves 39𝑚𝑊 power consumption for 8-bit TI- SAR ADC. Low power structure is designed and the desired target is reached according to results.

5.6 Figure of Merit

For data converters, a figure of merit (FoM) is defined to compare the power performances with different precision and speed. FoM of the designed ADC is calculated in equation 5.7.

𝐹𝑜𝑀 = 𝑃𝑡𝑜𝑡 2𝐸𝑁𝑂𝐵_{× 𝐹}

𝑆

61 6. CONCLUSION

In this thesis, low power 8-bit 2𝐺𝑆/𝑠 TI SAR ADC architecture is designed in 180𝑛𝑚 1.8𝑉 CMOS process. This TI-SAR ADC is suitable to be used in portable measurement devices.

The simulation across 36 corners and Monte Carlo analyses indicate that the TI SAR ADC achieves DNL level of 0.3𝐿𝑆𝐵, INL level of 0.4𝐿𝑆𝐵, 47𝑑𝐵 SNR, 55𝑑𝐵 SFDR, 47𝑑𝐵 SINAD, 7.55 ENOB at 2 𝐺𝐻𝑧 input frequency. It consumes 11𝑚𝑊 power. With the created ADC, the desired goal is achieved. The used 180𝑛𝑚 CMOS technology and the achieved results show the designed low power TI-SAR ADC is compatible for portable measurement devices.

63 REFERENCES

Akita, I., Furuta, M., Matsuno, J., & Itakura, T. (2011). A 7-bit 1.5-GS/s time- interleaved SAR ADC with dynamic track-and-hold amplifier. IEEE Asian

Solid State Circuits Conference, 293-296.

Arian, A., Saberi, M., & Hosseini Khayat, S. (2011). Successive Approximation ADC with Redundancy Using Split Capacitive-Array DAC. IEEE Iranian

Conference on Electrical Engineering, 1-4.

Bekal, A., Goswami, M., Singh, B. R., & Pal, D. (2014). A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC. IEEE

International Symposium on Electronic System Design, 219-223.

Chen, Y., Zhu, X., Tamura, H., Kibune, M., Tomita, Y., Hamada, T., . . . Kuroda, T. (2009). Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEEE Custom Integrated Circuits Conference, 279-282. Dlugosz, R., & Iniewski, K. (2007). Flexible Architecture of Ultra-Low-Power

Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks (Cilt 2007). New York: Hindawi

VLSI Design.

Du, L., Ning, N., Zhang, J., Yu, Q., & Liu, Y. (2013). Self-Calibrated SAR ADC Based on Split Capacitor DAC without the Use of Fractional-Value Capacitor.

IEEJ Transactions on Electrical and Electronic Engineering, 8, 408-414.

Fang, J., Thirunakkarasu, S., Yu, X., Silva-Rivas, F., Kim, K. Y., Zhang, C., & Singor, F. (2015). A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS. IEEE Custom Integrated Circuits, 1-4.

Ginsburg, B. P., & Chandrakasan, A. P. (2007). 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC. IEEE Journal of Solid-State Circuits,

42(4), 739-747.

Gregorian, R. (1999). Introduction to CMOS OP-AMPs and Comparators. WILEY. Greshishchev, Y., Aguirre, J., Besson, M., Gibbins, R., Falt, C., Flemke, P., . . .

and Wang, S. (2010). A 40GS/s 6b ADC in 65nm CMOS. International Solid-

State Circuits Conference Digest of technical Papers (ISSCC) (pp. 390-391).

San Francisco, CA: IEEE.

Greshishchev, Y., Aguirre, J., Besson, M., Gibbins, R., Falt, C., Flemke, P., . . . and Wang, S. (2010). A 40GS/s 6b ADC in 65nm CMOS. International Solid-

State Circuits Conference Digest of technical Papers (ISSCC) (pp. 390-391).

San Francisco, CA: IEEE.

Janssen, E., Doris, K., Zanikopoulos, A., Murroni, A., Weide, G. v., Lin, Y., . . . Fregeais, Y. (2013). An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS. IEEE International Solid-State Conference Digest of Technical

Papers, 464-465.

Kundu, S., Lu, J. H., Alpman, E., Lakdawala, H., Paramesh, J., Jung, B., . . . Gordon, E. (2014). A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-

64

interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN. IEEE

Custom Integrated Circuits Conference, 1-4.

Lee, S., Chandrakasan, A. P., & Lee, H.-S. (2014). A 1 GS/s 10b 18.9 mW Time- Interleaved SAR ADC With Background Timing Skew Calibration. IEEE

Journal of Solid-State Circuits, 46(12), 2846-2856.

Liu, C. C., Chang, S. J., Huang, G. Y., & Lin, Y. Z. (2009). A 0.92mW 10-bit 50- MS/s SAR ADC in 0.13 um CMOS process. IEEE Symposium on VLSI

Circuits Digest of Technical Papers, 236-237.

Liu, C. C., Chang, S. J., Huang, G. Y., & Lin, Y. Z. (2010). A 10-bit 50 MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE Journal of

Solid-State Circuits, 45(4), 731-740.

Maloberti, F. (2007). Data Converters. Dordrecht: Springer.

McCreary, J. L., & Gray, P. R. (1975). All-MOS Charge Redistribution Analog-to- Digital Conversion Techniques-Part 1. IEEE Journal of Solid-State Circuits,

10(6), 379-381.

Ozkaya, I. (2010). Wide Input Signal Range 14 bits 1 MSPS SAR ADC in 0.35μm High

Voltage CMOS Process. Institute of Science and Technology, Electronics and

Communication Engineering. Istanbul: Istanbul Technical University VLSI Laboratory.

Razavi, B. (1995). Principles of Data Conversion System Design. New York: IEEE Press.

Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. New York: McGraw- Hill.

Razavi, B., & Wooley, B. A. (1992). Design techniques for high-speed, high resolution comparators. IEEE Journal of Solid-State Circuits, 27(12), 1916- 1926.

Schvan, P., Bach, J., Falt, C., Flemke, P., Gibbins, R., Greshishchev, Y., . . . Wolczanski, J. (2008). A 24GS/s 6b ADC in 90nm CMOS. International

Solid-State Circuits Conference (ISSCC) (pp. 544-634). San Francisco, CA:

IEEE.

Shinagawa, M., Akazawa, Y., & Wakimoto, T. (1990). Jitter Analysis of High- Speed Sampling System. IEEE Journal of Solid-State Circuits, 25(1), 220-224. Son, W. L., Majid, H. A., & Musa, R. (2012). High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC. World Academy of

Science, Engineering & Technology(72), 421-424.

Suarez, R. E., Gray, P. R., & Hodges, D. A. (1975). All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part 2. IEEE Journal of Solid-State

Circuits, 10(6), 379-385.

Tabasy, E., Shafik, A., Lee, K., Hoyos, S., & Palermo, S. (2013). A 6b 10GS/s TI- SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS. VLSI

Circuits, C274-C275.

Talekar, S. G., Ramasamy, S., Lakshminarayanan, G., & Venkataramani, B. (2009). A low power 700MSPS 4bit time interleaved SAR ADC in 0.18um CMOS. IEEE Region 10 Conference TENCON, 1-5.

Tual, S. L., Singh, P. N., Curis, C., & Dautriche, P. (2014 ). 22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology. IEEE International Solid-State Circuits Conference Digest

65

Verbruggen, B., Iriguchi, M., & Craninckx, J. (2012). A 1.7 mW 11b 250 MS/s 2- Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE Journal of Solid-State Circuits, 47(12), 2880-2887.

Xu, W., & Friedman, E. G. (2002). Clock Feedthrough in CMOS Analog Transmission Gate Switches. IEEE International ASIC/SOC Conference, 181- 185.

Yee, Y. S., Terman, L. M., & Heller, L. G. (1979). A two-stage weighted capacitor network for D/A-A/D conversion. IEEE Journal of Solid-State Circuits, 14(4), 778-781.

67

APPENDIX A - MATLAB CODE FOR DAC INL&DNL CALCULATION

dacoutfile = 'dacinldata.csv'; A = csvread(dacoutfile); dacout=[]; for i=1:15:size(A,1) for j=i:i+7 dacout=[dacout;A(j,2)]; end end n=8; bincountup=dec2bin(0:2^n-1)-'0'; %%---IDEAL ... DAC--- for i=1:n index(i,1)=2^(n-i); end

deccountup=bincountup*index; %calculate adc decimal output

lsb=(((dacout(end)-(dacout(1))))/((size(dacout,1)-1))); idealout=(deccountup*lsb)+dacout(1);

difference=idealout-dacout; inl=difference/lsb;

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APPENDIX B - MATLAB CODE FOR ADC INL&DNL CALCULATION

clc

clear all

adcoutfile = './adcinldata.csv';

adcout = csvread(adcoutfile,1,1); %read sim results from file

adcout=adcout/3.90625e-3;

dnl = hist(adcout,min(adcout):max(adcout)) / (numel(adcout)/(max(adcout)-min(adcout)+1)) - 1;

inl=cumsum(dnl); %calculate INL

figure(1);

plot(dnl,'DisplayName','dnl','YDataSource','dnl');figure(gcf);

figure(2);

71 CURRICULUM VITAE

Name Surname : Busra TAS

Date of Birth : 21.06.1990

E-Mail : [email protected]

Education

B.Sc : Electrical and Electronics Engineering at TC. Maltepe University, Istanbul

Professional Experience

: Research Assistant of TUBITAK (The Scientific and Technological Research Council of Turkey) (July.2014 – June.2015)