2.2.1 Multi-Vdd
This technique is based on the premise that not all parts of the chip need to work at the same speed [44]. As mentioned in the introduction, the System-on-Chip (SoC) may contain several peripherals apart from the Central Processing Unit (CPU) cores that can run at different speeds. Therefore their supply voltage Vdd could be lowered and still meet timing requirements. Therefore its Dynamic (and Leakage) power could be lowered.
2.2.2 DVFS
Another widely used technique for reducing power consumption is DVFS, or also com-monly found in the literature as Dynamic Voltage Scaling (DVS). This technique aims
to reduce power by reducing the voltage supply of the device (or the core) at the ex-pense of reducing the frequency of the clock signal. This reduction of frequency is done because of gate switching latency. By reducing the voltage it can be seen in Section 2.1 that overall power consumption gets reduced. By reducing the clock frequency the device reduces its performance as computations are directly dependent on the operating frequency, so this technique is most effective when maximum performance is not needed.
Then, in order to use DVFS effectively, techniques have been designed to reduce power with the aim of penalising performance at the very least. These include the simple detection of what the workload is at a particular moment, to predict what the workload will be in the future. Other techniques are aimed to particular types of applications such as multimedia and videogames, where performance constraints are fixed in order to provide a desired quality.
Depending on the device, the DVFS implementation may be defined as either a discrete compact number of voltage-frequency pairs e.g. Intel’s XScale PXA270 processor [45];
or as an adaptable range of frequencies with an adaptable range of voltages, as the one implemented by Nakai et al. [46]. This review focuses more on the former, as future implementations of algorithms following this report will be based in voltage-frequency pairs (from now on called V-F pairs or V-F setting).
2.2.3 PG
Dynamic Power Management (DPM) is a technique widely employed in microprocessors and other electronic devices, such as Hard Disk Drives (HDDs) and other peripherals.
The process of DPM consists of taking advantage of idle times of the device (e.g. pro-cessor, HDD) between workloads, by setting the device to an available low power mode.
Low power modes vary among devices, e.g. IBM’s Travelstar HDD has 5 low power modes (plus active power modes)[6], the microprocessor StrongARM SA-1100 [6] has 3 power modes: ACTIVE, IDLE and SLEEP.
Normally there is an important trade-off between the power consumption (or power saving) in a particular power mode and the time and power it takes to transition to/from that power mode, meaning that the deeper sleep level i.e. the more power savings, the longer the transition time there is. Therefore the decision to go to a low power state mode should be based on the idle time available for the device before a workload arrives.
In most cases (but not all) the power consumption for doing the transition to a low power state is higher than the power consumed when idle. A term is then defined as the Break-Even Time TBE which is the amount of time the device should spend in the low power mode plus the transition time, for the energy consumption to be the same as the device in IDLE mode [6]. For simple explanation of the terms it will be assumed that a device has 3 power modes: ACTIVE, IDLE and SLEEP.
In microprocessors, the SLEEP mode reduces power consumption compared to just being IDLE, as several modules and clocks of the processor get disabled when sleeping.
Ideally as soon as a workload is finished and the processor stops being ACTIVE, it would enter SLEEP mode. In reality, there is a transition period between ACTIVE/IDLE to SLEEP as well as from SLEEP to ACTIVE. Some processors have several sleep modes. For example, Texas Instruments’ DM3730 processor [47] has 5 power states:
Active, Inactive, Retention with logic on in low-voltage, Retention with logic off, and Off. Normally, the deeper the sleep level in a processor, the higher the overhead is, both in terms of time and consequently energy. These overheads are important to decide if it is worth going to a SLEEP mode. The Break Even Time is the minimum time the processor needs to be asleep for it to be worth going into sleep mode.
Time
Power
TACTIVE TIDLE TACTIVE TTOFF TSLEEP TTON TACTIVE
PACTIVE
PIDLE
PTOFF
PACTIVE PACTIVE
PTON
PSLEEP
Figure 2.5: Definitions of power and times for a device with IDLE and SLEEP modes
In order to explain better what the Break Even Time TBE is, Figure 2.5 shows the different powers and times under the different power modes and the transitions. Let
PACT IV E be the power consumption when the processor is ACTIVE and the time at
this state TACT IV E. In the same manner, PIDLE is the power when the processor is IDLE, and the time at this state is TIDLE. The energy consumed at ACTIVE and IDLE periods are EACT IV E and EIDLE respectively:
EACT IV E= PACT IV ETACT IV E EIDLE = PIDLETIDLE (2.16)
For SLEEP mode there is a transition period TT R, which is the sum of the time it takes to go to sleep TOF F and to wake up TON, which in turn these transitions dissipate power, POF F and PON respectively. The sleep and wake up transitions are constant in terms of time and power, the energy it takes to transition ET R is then fixed:
TT R= TT OF F + TT ON ET R= TT OF FPT OF F + TT ONPT ON (2.17)
After the processor has gone to sleep, the power consumption PSLEEP during the time TSLEEP is the energy consumed ESLEEP:
ESLEEP = TSLEEPPSLEEP (2.18)
Therefore, in order for the transition to the SLEEP mode to be worth it, it is necessary that the energy during sleeping ESLEEP and the transition energy ET Rbe less than the energy without going to sleep i.e. when being IDLE, this is EIDLE:
EIDLE ≥ ET R+ ESLEEP (2.19)
The Break Even Time TBE then substitutes the TIDLE, so now TBE needs to be calculated:
PIDLETBE = ET R TT R
TT R+ PSLEEPTSLEEP (2.20)
And as the TIDLE is the time used for sleeping with the transitions, TSLEEP becomes:
TIDLE = TBE = TT R+ TSLEEP → TSLEEP = TBE− TT R (2.21)
Substituting Equation 2.21 in Equation 2.20:
PIDLETBE = ET R
TT RTT R+ PSLEEP(TBE− TT R) (2.22)
Solving for TBE:
TBE = TT R
ET R
TT R − PSLEEP
PIDLE − PSLEEP (2.23)
Based on this concept, the determining factor for deciding to go to SLEEP is then to know if TIDLE > TBE. As in a microprocessor this value is not known a priori, different techniques have been developed to estimate what TIDLE will be before really knowing it.
Benini et al. [6] provides a thorough review of different implementations of DPM tech-niques and their advantages. To provide some context for more complex techtech-niques explained later, some of the basic DPM techniques of the reference are explained here.
DPM techniques for microprocessors are mainly divided into Predictive and Stochastic Techniques.