A Power Model for Intel SCC

Accurate thermal simulation requires detailed power traces for each floorplan block.

As we can see from the floorplan there are the following basic blocks:

• CPU cores.

• DRAM controllers.

• Router + Clock.

• Serial interface engine (SIF) I/O.

We can obtain the power break-down for these blocks from [60]. In table2.1, we show the values for two extreme stress workloads.

From Table2.1we see that the main contribution to the total power is given by the CPU and the DRAM controllers. Unfortunately, the power probes available on SCC are not sufficient to probe directly the power consumption of each functional unit.

Indeed the available probes are:

Table 2.2: Workloads used for stressing SCC. (One cache line of SCC is 32 bytes).

Workload Description

L1 16 KB circular buffer size.

Data increment of 32 Bytes (1 cache line).

L2 32 KB circular buffer size.

Address increment of 32 Bytes (1 cache line).

L2-2Access 32 KB circular buffer size.

Address increment of 16 Bytes (2 access for cache line).

DRAM 4 MB circular buffer size.

Address increment of 32 Bytes (1 cache line).

DRAM-2Access 4M B circular buffer size.

Address increment of 16 Bytes (2 access for cache line).

• Analog portion of DRAM memory controller.

• Digital portion of DRAM memory controller and SIF.

• CPU cores, Routers and global clocking.

We first evaluate the sensibility of these probes to different levels of utilization of SCC.

We then create a power model suitable to estimate the power consumption of each CPU core given its utilization and workload properties. This will allow us to feed each func-tional unit in the thermal floorplan with the proper power traces. The different stress patterns are obtained by executing different sets of synthetic benchmarks. Each syn-thetic benchmark is made-up of an infinite loop where an ALU operation is executed on a circular data buffer. The dimension of the circular buffer increases within dif-ferent benchmarks: moving from 16 KB to 4 MB. At each iteration it is executing a read-write to an entry of circular buffer that moves with an incremental step of one cache-line. By doing that, the various synthetic benchmarks are capable of hitting always a data in the L1 cache, missing the L1 cache but hitting the L2 cache and miss-ing L1, L2 and hittmiss-ing the DRAM. These generate different memory stress patterns.

Table2.2describes workloads properties of different synthetic benchmarks.

0 2 4 6 8 10 12

no. active cores in quarter

core power

Core power vs number of active cores (533MHz)

L1 L2−2Access L2

DRAM−2Access DRAM

Figure 2.3: Core power consumption with number of active cores in each cluster for each of the workloads. Dots are measured data; Lines are the result of linear fitting.

2.4.1.1 SCC Power Measurement

The first analysis we performed has highlights how the core power changes in between different cores and workload under stable conditions. To do that, we divided SCC into 4 quarters of 12 cores each. Then for each of them we increase the number of active cores. We repeat this test for different synthetic benchmarks. As can be seen in Figure2.3, the power increases linearly with the number of active cores for all of the stress workloads. This suggests that the contribution of the core power to the total chip power consumption is independent of the core position. Thus for the workload used, superposition principle is valid and we can obtain the single core power by dividing the total power to the number of cores.

The second test aims to highlight the effect of frequency scaling on different bench-marks. Figure2.4shows the cores power consumption when all of them are executing the same benchmark while scaling the tile frequencies. We can notice that the power changes linearly with the frequency with different slopes for each benchmark. Intu-itively this is due to the different CPU-usage of the different synthetic benchmark.

A common metric of CPU-load [39] is the Clock Per Instruction (CPI). This can be

150 200 250 300 350 400 450 500 550

Core power consumption with frequency

freq

Figure 2.4: Core power consumption for each workload for different frequency values.

Dots are measured data values. Lines are the result of linear fitting.

directly measured at run-time by using the performance counters.

Figure2.5shows the CPI of the different benchmarks while changing the tile fre-quency. We can notice that for L2 and L1 benchmarks the CPI does not change with the frequency. This suggests that both the L1 and L2 are in the same clock domain of the tile. For the DRAM benchmark instead the CPI scales with the frequency and the slope is not constant but changes itself with the frequency.

These effects can be explained by looking at the digital part of DRAM controller power consumption as shown in Figure 2.6. We notice the same effect. Indeed the power of the DRAM controller shows a saturation effect at higher frequency. This can be explained by bandwidth saturation due to the higher memory accesses issued at higher frequencies.

2.4.1.2 Power Model for SCC CPU Cores

We combine the core power data values, to derive a power model suitable to predict the core power consumption under different workload and tile frequency. For each core the power consumption can be split in two main contributions: the idle power and

150 200 250 300 350 400 450 500 550 0

10 20 30 40 50 60

Average CPI value vs frequency

freq

CPI

L1 L2−2Access L2

DRAM−2Access DRAM

Figure 2.5: Changes of CPI for different values of frequency and different workloads.

150 200 250 300 350 400 450 500 550

3.6 3.7 3.8 3.9 4 4.1 4.2 4.3

freq

dram controller power

DRAM controller power vs number of active cores

1 core active 12 cores active

Figure 2.6: Power consumption of DRAM controllers as a function of frequency and number of active cores running.

the active power (P_core= P_active+ P_idle). Whereas P_idlecan be modeled as a function of only the frequency (P_idle= g( f_core)), the active one can be modeled as a function of CPI and frequency (P_active= g(CPI_core, f_core)). As a result, idle power can be effectively modeled as linear regression of the core clock frequency (P_idle= b + a. f_core). Using the experimental data a values a = 0.35 × 10⁻³ and b = 0.3872 are obtained. By using equation2.3as the fitting function, a closed form model can be generated for the per-core active power.

g(CPI, f ) = (a + b.CPI^c). f + d + (a⁰+ b⁰.CPI^c0). f (2.3) In equation 2.3, g(CPI, f ) is the per-core active power value. We use a least square optimization algorithm to find the optimal coefficients that minimizes the error value between estimated and real data. Values of a = 0.0131, b = −0.240, c = 0.085, d = 0.021, a⁰= 0.0131, b⁰= 0.215 and c⁰= 0.02 are obtained for the coefficients of equation2.3as result. Figure2.7shows the fitting performance. Since no performance counters are available in SCC to probe on-line the DRAM usage, we decided to use directly the power measurement of the dram controller as input to the thermal model.

We feed each memory controller floorplan block in the thermal simulation with 1/4 of the measured DRAM controller power consumption.