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V_R gradually through the path consisting of N3 and N5. At the same time, BL’ stays at
VDD/2. V_R sweeps gradually from VDD/2 to 0V. After the data of BL and BL’ has been
sensed by the sense amplifier, the signal RL can be switched to zero and thus to cut off N3 and N4. BL then needs to be re-charged to VDD/2 to prepare for future reading or writing
operations. It is worth mentioning that, in non-adiabatic mode, the power source V_R can be set to a constant level, which is lower than 0.5V, i.e. 0.3V, because when reading is completed, the 0.2V voltage difference between BL and BL’ is sufficient for the sense amplifier to produce the correct results (the minimal requirement is 0.1V).
4.3.2.3 Advantages Over the Proposed 8T SRAM
The proposed 8T SRAM cell has two big disadvantages. Firstly, as only PMOS transistors (P4, P5 and P6 in Fig.4.3 (a)) are used for reading data, the discharge on bit-line is very slow due to the poor performance of PMOS when it needs to pass a zero. Moreover, the voltage difference between two the bit-lines BL and BL’ may not be large enough to be detected by the sense amplifier, which could generate a reading fault. Secondly, when 45nm (or lower) technology node is used, after hundreds of times of reading the data from this memory cell, one internal node which holds ‘0’ would eventually be charged up by the leakage current, which could cause errors. This is because the leakage current is high in the deep submicron region, caused by the shrinking length of transistors and also the reduction of the thickness of gate oxide. The gate oxide leakage current is much higher when a transistor is On than when it is Off. If using PMOS transistors for the reading sub-circuit, the internal node which holds a low voltage value always turns on a PMOS transistor whose gate is connected to this internal node. Under this circumstance, gate oxide leakage current is high. The proposed 9T design addresses this issue by using NMOS transistors instead and thus the memory could be still readable even after thousands of cycles. Moreover, the reading speed is much faster than that of the proposed 8T architecture. However, after to some IC companies, fabrication seems the only way to prove the feasibility of these structures.
4.4 Power Saving Strategy
The dynamic and static power have been two major sources of the total power consumption of a circuit. In an SRAM array, the dynamic power is consumed not only by the SRAM cell but also by the capacitor of the bit-lines. Due to the high capacitance, usually the major part
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of dynamic power is dissipated on bit-lines. As mentioned in Chapter 2, adiabatic logic can dramatically save the dynamic power by limiting the current flow at the expense of performance. Furthermore, once the transistor is turned on, the energy flows through it in a gradual and smooth manner not abruptly switching from 0 to VDD (and vice-versa) as in static
CMOS logic. In this way, the current will be very small, which results in low power consumption. In order to implement this type of logic into the memory design, the two proposed SRAM cells are divided into two separate parts.
In writing mode, thanks to the introduction of the PMOS P3 in Fig.4.2, I ensure that the voltage both inside and outside of the memory cell is balanced before a write operation starts although there is a small amount of power consumed during sharing. Hence, the adiabatic principles are satisfied. Regarding the reading operation, firstly, full-swing pre-charging is avoided and with a dramatic energy saving. Secondly, V_R provides adiabatic reading behavior when voltage distribution is applied. Even in the non-adiabatic mode, since the proposed SRAM cell works with the half-swing principle, it can still save power for both write and read operations.
On the other hand, static power, which is often neglected in sub-micron ( below 1µm) CMOS processes, starts to dominate the total power consumption in some applications which use deep submicron underlying processes, while memory blocks usually have the most leakage power consumption due to their high density/area. Static power is mainly caused by sub- threshold current and gate leakage current, which are proportional to VDS (Drain Source
Voltage) and gate oxide thickness respectively. Having no control over the process parameters, reducing VDS is my main approach to achieve low static power. It can be
observed from the two proposed designs (Fig.4.3) that there is no direct ground connection in the SRAM cells along with the balanced voltage distribution in idle mode, hence the standby power can be reduced to an extremely low level. The power results will be discussed next in Section 4.6.
4.5 Write and Read Simulations
Besides the low power constraint, high stability to variations and low error during write and read operations are also highly desirable in SRAM design. The static noise margin (SNM) is considered to be the standard measure of the stability of a SRAM cell while write-trip-point