4.5 Power Sensitivity Analysis
4.5.2 Power Sensitivity Method to Estimate Minimum/Maximum Average Power
In previous section, Power Sensitivity Estimation (PSE) can estimate power sensitivity as a by product of average power estimation with nominal values of signal probability and activity. The minimum and maximum average power of a circuit can easily be computed as follows [Chen97], [Chen98]:
∑
∆ − Φ = Φ s allPI i a i avg i a ' min εξ
(4.38)∑
∆ − Φ = Φ s allPI i a i avg i a ' max εξ
(4.39)Where Φavg is the average normalized power dissipation measure (proportional to the switched capacitance). It can be estimated during the average power estimation process using PSE with nominal values of primary input signal properties. The term ξai
is the power sensitivity to ai of primary input i; ∆ai is the activity variation. Since the statistical techniques to estimate power can handle different delay models for logic gates, PSE can also handle different delay models and includes spurious transitions in its analysis. Fig. 4.4 gives the flow of the power sensitivity technique to obtain minimum and maximum average power dissipation.
To compare the results obtained by simulation with those obtained by PSE, we compute the percentage difference using the expression in [Chen97], [Chen98]:
Fig. 4.4 Power sensitivity technique to obtain bound average power
Start
Generate a random circuit state
Generate input vector pair V ,0 V T Simulate the circuit to obtain
(
V V T)
Power 0 Multiply Power(
V 0VT)
by(
)
(
)
i T i i I I P θ ∂ ∂ln 0 Converge?Obtain bounds for average power
End
No
Chapter 4 Monte Carlo simulation method
(
)
(
)
(
)
∑
∑
− s allPI a s allPI a a SIM PSE SIM i i i ' 'ξ
ξ
ξ
(4.40)where ξai (PSE) is the power sensitivity obtained by PSE and ξai (SIM) is the power
sensitivity obtained by simulation. Since the long run simulation method repeats the estimation procedure n+1 times (n is the number of primary inputs), execution time may be unacceptably long for large n.
After obtaining power sensitivities, we use (4.38) and (4.39) to compute the minimum and maximum average power for each simulated circuit. For simplicity, all primary inputs are assumed to have the same activity variation of ±0.05 and there is no probability variation for each primary input. However, the method is not limited to such assumptions.
4.6 Conclusions
In this chapter we have presented a Monte Carlo simulation methodology to estimate the average power consumption of digital circuits. This methodology determines that how the samples are selected and subsequently, how many samples are required for the convergence. Therefore, the term efficiency should be referred to as the product of simulation effort spent on each sample (or sample granularity) times the number of required sample, instead of strictly the number of required sample. After investigating the efficiency and over sampling characteristics of Monte Carlo simulation, we conclude that Monte Carlo simulation strategy favors small sample granularity. In other words, if sample granularity is a choice, smaller sample granularity achieves higher overall efficiency. Accurate estimation of power dissipation is critical in evaluating and synthesizing designs for low power at various levels of abstraction. This approach achieves good accuracy in reasonable time, neglecting trade-off between speed or accuracy of probabilistic techniques. Probabilistic techniques suffer trade-off between speed or accuracy because they must resolve the correlations between internal circuit nodes. If correlations are taken into account, these methods can be accurate. However, it is computationally expensive and impractical. Therefore, fast implementations of these techniques are necessarily inaccurate.
Chapter 5 Power macro-modelling for IP designs
Chapter 5
Chapter 5 Power macro-modelling for IP designs
Chapter 5
Power macro-modelling for IP designs
Table of contents
5 Power macro-modelling for IP designs ...103 5.1 Introduction...106 5.2 Power Macro-modelling Challenges for Soft IP Core ...107 5.3 Fundamental Requirements for RTL Power Macro-modelling ...108 5.4 Problem Formulation...109 5.5 Proposed Power Macro-modelling Methodology ...111
5.5.1 Input Macro-modelling for IP-based Macro-blocks ... 112 5.5.2 Output Macro-modelling for IP-based Macro-blocks... 114 5.5.3 Power Macro-modelling for IP-based Digital System... 115 5.5.4 Macro-model Construction... 115
5.6 Linear Regression Macro-modelling ...121
5.6.1 Variable Selection ... 123 5.6.2 Representation of Statistical Parameters as Linear Regression Variables ... 129
5.7 Macro-model Quality Analysis ...130 5.8 Conclusions ...132
In this chapter we focus on the problem of power macro-modelling methodology at RTL for estimating the power consumption of IP-based designs in the context described in chapters 1, 2, 3, 4.
5.1 Introduction
The power macro-modelling is a promising solution to the problem of high-level power estimation. Recently RTL power modelling has defined an estimation paradigm that has been shown to be superior to any other, in terms of robustness, accuracy and flexibility [Liu05]. The paradigm relies on a view of the RTL description as a set of instantiated IP macro-block (such as comparators, multipliers, adders), or more complex macro-blocks (such as counters, shift registers). Beside these blocks, RTL description includes also a finite state machine. In [Chen97], the model fits nicely into the FSM with data-path model and is common to all the estimation approaches based on macro-modelling. RTL power estimation amounts to the construction of accurate power macro-models for macro-blocks that estimates the total power consumption of the design, which simply consist of summing all the contributions given by the individual power models.
The urgent need of a feasible IP power model is becoming more useful in recent years. However, it has been proven that the macro-modelling is effective for individual IP components [De99]. The application of power macro-modelling on IP blocks of the system requires knowledge of the signal statistics among different IP blocks. To obtain this information, the design architect must perform different functional simulations.
A simulation approach at high-level power estimation is to functionally simulate one circuit and to collect input sequences for each module/macro-blocks. In other words, the macro-model is to generate a mapping between the power dissipation of a circuit and certain statistics of input signals. Finally, the power dissipation of all the blocks is added together to get power consumption of the whole design. A good macro-model must be able to determine the power under different primary input distributions. Since power dissipation of a circuit is strongly dependent on the statistics of primary inputs, the relationship of power verses primary input probabilities and switching activities is complicated surfaces. Once such a surface is setup, power dissipation under different distributions of primary inputs can be easily obtained. However, to construct such a
Chapter 5 Power macro-modelling for IP designs
power surface, a large number of discrete points are required. If one chooses p representative values for the probability and activity of each primary input, the number of representative points in the specification-space can be
n
p2
(n is the number of primary inputs). Hence, to generate the power surface, a symbolic or statistical power estimation process has to be repeated p n
2
times.
The macro-model for the components may be parameterized in terms of the input bit width, the internal organization/architecture of the component, and the supply voltage level. In some cases the macro-model can be done analytically using the information about the structure of the gate-level description of the modules, without resorting to simulation as proposed in [Benini98]. Various RTL power macro-modelling techniques have been introduced previously [Liu05], [Chen97], [Moudgill99]. Among those techniques regression-based power models are particularly attractive because they are general (they are applicable to any macro), they are flexible (they represent families of models that offer to the designer different trade-offs between model complexity, characterization effort and accuracy) and they can be built automatically (without human intervention).