PROGRAM FOR RADIX-4 MULTIPLIER Using Ripple Carry Adder

IMPLEMENTATION AND RESULTS

 RESULTS FROM POWER ANALYSIS

5.1 PROGRAM FOR RADIX-4 MULTIPLIER Using Ripple Carry Adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity R4MUL_RCA is

Port (a, b : in STD_LOGIC_VECTOR (31 downto 0); mul: inout std_logic_vector(63 downto 0);

overflow: out std_logic); end R4MUL_RCA;

architecture Behavioral of R4MUL_RCA is component RADIX4_ENCODER is

Port ( x : in STD_LOGIC_VECTOR (31 downto 0); arg : in STD_LOGIC_VECTOR (2 downto 0);

pp : inout STD_LOGIC_VECTOR (63 downto 0)); end component;

component fulladder

Port (a, b, cin: in STD_LOGIC; sum, cout: out STD_LOGIC); end component;

component RCA64 is

Port (a, b: in STD_LOGIC_VECTOR (63 downto 0) ; add: out STD_LOGIC_VECTOR (63 downto 0); cout: out STD_LOGIC);

end component;

signal arg1, arg2, arg3, arg4: std_logic_vector(2 downto 0); signal arg5, arg6, arg7, arg8: std_logic_vector(2 downto 0);

signal arg9, arg10, arg11, arg12: std_logic_vector(2 downto 0); signal arg13, arg14, arg15, arg16: std_logic_vector(2 downto 0); signal tt: std_logic_vector(32 downto 0);

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15:

std_logic_vector(63 downto 0);

signal sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8: std_logic_vector(63 downto 0);

signal sum9,sum10,sum11,sum12,sum13,sum14,sum15: std_logic_vector(63 downto 0);

signal y: std_logic_vector(15 downto 0);

signal pp1, pp2, pp3, pp4, pp5, pp6, pp7, pp8 : STD_LOGIC_VECTOR (63 downto 0);

signal pp9, pp10, pp11, pp12, pp13, pp14, pp15, pp16: STD_LOGIC_VECTOR (63 downto 0);

begin

tt<= a(31 downto 0)&'0'; arg1<=tt(2 downto 0); arg2<=tt(4 downto 2); arg3<=tt(6 downto 4); arg4<=tt(8 downto 6); arg5<=tt(10 downto 8); arg6<=tt(12 downto 10); arg7<=tt(14 downto 12); arg8<=tt(16 downto 14); arg9<=tt(18 downto 16); arg10<=tt(20 downto 18); arg11<=tt(22 downto 20); arg12<=tt(24 downto 22); arg13<=tt(26 downto 24); arg14<=tt(28 downto 26); arg15<=tt(30 downto 28); arg16<=tt(32 downto 30);

u2: RADIX4_ENCODER port map(b(31 downto 0), arg2, pp2); u3: RADIX4_ENCODER port map(b(31 downto 0), arg3, pp3); u4: RADIX4_ENCODER port map(b(31 downto 0), arg4, pp4); u5: RADIX4_ENCODER port map(b(31 downto 0), arg5, pp5); u6: RADIX4_ENCODER port map(b(31 downto 0), arg6, pp6); u7: RADIX4_ENCODER port map(b(31 downto 0), arg7, pp7); u8: RADIX4_ENCODER port map(b(31 downto 0), arg8, pp8); u9: RADIX4_ENCODER port map(b(31 downto 0), arg9, pp9); u10: RADIX4_ENCODER port map(b(31 downto 0), arg10, pp10); u11: RADIX4_ENCODER port map(b(31 downto 0), arg11, pp11); u12: RADIX4_ENCODER port map(b(31 downto 0), arg12, pp12); u13: RADIX4_ENCODER port map(b(31 downto 0), arg13, pp13); u14: RADIX4_ENCODER port map(b(31 downto 0), arg14, pp14); u15: RADIX4_ENCODER port map(b(31 downto 0), arg15, pp15); u16: RADIX4_ENCODER port map(b(31 downto 0), arg16, pp16);

s1<= pp2(61 downto 0)&"00"; s2<= pp3(59 downto 0)&"0000"; s3<= pp4(57 downto 0)&"000000"; s4<= pp5(55 downto 0)&"00000000"; s5<= pp6(53 downto 0)&"0000000000"; s6<= pp7(51 downto 0)&"000000000000"; s7<= pp8(49 downto 0)&"00000000000000"; s8<= pp9(47 downto 0)&"0000000000000000"; s9<= pp10(45 downto 0)&"000000000000000000"; s10<= pp11(43 downto 0)&"00000000000000000000"; s11<= pp12(41 downto 0)&"0000000000000000000000"; s12<= pp13(39 downto 0)&"000000000000000000000000"; s13<= pp14(37 downto 0)&"00000000000000000000000000"; s14<= pp15(35 downto 0)&"0000000000000000000000000000"; s15<= pp16(33 downto 0)&"000000000000000000000000000000";

42 h1: RCA64 port map(pp1, s1, sum1, y(0)); h2: RCA64 port map(sum1, s2, sum2, y(1)); h3: RCA64 port map(sum2, s3, sum3, y(2)); h4: RCA64 port map(sum3, s4, sum4, y(3)); h5: RCA64 port map(sum4, s5, sum5, y(4)); h6: RCA64 port map(sum5, s6, sum6, y(5)); h7: RCA64 port map(sum6, s7, sum7, y(6)); h8: RCA64 port map(sum7, s8, sum8, y(7)); h9: RCA64 port map(sum8, s9, sum9, y(8)); h10: RCA64 port map(sum9, s10, sum10, y(9)); h11: RCA64 port map(sum10, s11, sum11, y(10)); h12: RCA64 port map(sum11, s12, sum12, y(11)); h13: RCA64 port map(sum12, s13, sum13, y(12)); h14: RCA64 port map(sum13, s14, sum14, y(13)); h15: RCA64 port map(sum14, s15, mul, overflow); end Behavioral;

Using Carry Look-Ahead Adders

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity r4mulcla is

Port ( a, b : in STD_LOGIC_VECTOR (31 downto 0); mul: inout std_logic_vector(63 downto 0);

overflow: out std_logic); end r4mulcla;

architecture Behavioral of r4mulcla is component r4encoder is

arg : in STD_LOGIC_VECTOR (2 downto 0);

pp : inout STD_LOGIC_VECTOR (63 downto 0)); end component;

component cla is

Port ( p,g : in STD_LOGIC_VECTOR (7 downto 0); cin: in std_logic;

sum : out STD_LOGIC_VECTOR (7 downto 0)); end component;

component PG_gen is

Port ( p, g : in STD_LOGIC_VECTOR (7 downto 0); iP, iG : out STD_LOGIC);

end component;

component carrygen is

Port ( p, g : in STD_LOGIC_VECTOR (7 downto 0); c1 : in STD_LOGIC;

c0 : out STD_LOGIC_VECTOR (7 downto 0)); end component;

component cla_64bit is

Port ( a, b : in STD_LOGIC_VECTOR (63 downto 0); cin: in STD_LOGIC;

sum : out STD_LOGIC_VECTOR (63 downto 0); cout : out STD_LOGIC);

end component;

signal arg1, arg2, arg3, arg4: std_logic_vector(2 downto 0); signal arg5, arg6, arg7, arg8: std_logic_vector(2 downto 0); signal arg9, arg10, arg11, arg12: std_logic_vector(2 downto 0); signal arg13, arg14, arg15, arg16: std_logic_vector(2 downto 0); signal tt: std_logic_vector(32 downto 0);

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15:

std_logic_vector(63 downto 0);

signal sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8: std_logic_vector(63 downto 0);

signal sum9,sum10,sum11,sum12,sum13,sum14,sum15: std_logic_vector(63 downto 0);

signal pp1, pp2, pp3, pp4, pp5, pp6, pp7, pp8 : STD_LOGIC_VECTOR (63 downto 0);

signal pp9, pp10, pp11, pp12, pp13, pp14, pp15, pp16: STD_LOGIC_VECTOR (63 downto 0);

signal y: std_logic_vector(15 downto 0); signal c1:std_logic;

begin c1<='0';

u1: r4encoder port map(b(31 downto 0), arg1, pp1); u2: r4encoder port map(b(31 downto 0), arg2, pp2); u3: r4encoder port map(b(31 downto 0), arg3, pp3); u4: r4encoder port map(b(31 downto 0), arg4, pp4); u5: r4encoder port map(b(31 downto 0), arg5, pp5);

u6: r4encoder port map(b(31 downto 0), arg6, pp6); u7: r4encoder port map(b(31 downto 0), arg7, pp7); u8: r4encoder port map(b(31 downto 0), arg8, pp8); u9: r4encoder port map(b(31 downto 0), arg9, pp9); u10: r4encoder port map(b(31 downto 0), arg10, pp10); u11: r4encoder port map(b(31 downto 0), arg11, pp11); u12: r4encoder port map(b(31 downto 0), arg12, pp12); u13: r4encoder port map(b(31 downto 0), arg13, pp13); u14: r4encoder port map(b(31 downto 0), arg14, pp14); u15: r4encoder port map(b(31 downto 0), arg15, pp15); u16: r4encoder port map(b(31 downto 0), arg16, pp16);

h1: cla_64bit port map(pp1, s1, c1, sum1, y(0)); h2: cla_64bit port map(sum1, s2, c1, sum2, y(1)); h3: cla_64bit port map(sum2, s3, c1, sum3, y(2)); h4: cla_64bit port map(sum3, s4, c1, sum4, y(3));

h5: cla_64bit port map(sum4, s5, c1, sum5, y(4)); h6: cla_64bit port map(sum5, s6, c1, sum6, y(5)); h7: cla_64bit port map(sum6, s7, c1, sum7, y(6)); h8: cla_64bit port map(sum7, s8, c1, sum8, y(7)); h9: cla_64bit port map(sum8, s9, c1, sum9, y(8)); h10: cla_64bit port map(sum9, s10, c1, sum10, y(9)); h11: cla_64bit port map(sum10, s11, c1, sum11, y(10)); h12: cla_64bit port map(sum11, s12, c1, sum12, y(11)); h13: cla_64bit port map(sum12, s13, c1, sum13, y(12)); h14: cla_64bit port map(sum13, s14, c1, sum14, y(13)); h15: cla_64bit port map(sum14, s15, c1, mul, overflow); end Behavioral;

Modified Booth Encoder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RADIX4_ENCODER is generic(N: integer:= 32);

Port ( x : in STD_LOGIC_VECTOR (N-1 downto 0); arg : in STD_LOGIC_VECTOR (2 downto 0);

pp : inout STD_LOGIC_VECTOR (2*N-1 downto 0)); end RADIX4_ENCODER;

architecture Behavioral of RADIX4_ENCODER is begin

process(arg, x)

variable temp, temp1, temp2: std_logic_vector(N downto 0); begin

47 if x(N-1)='1' then

temp:= '1'&x(N-1 downto 0); else

temp:= '0'&x(N-1 downto 0); end if;

if(arg="001"or arg="010") then temp1:= temp;

elsif(arg="101" or arg="110") then temp1:= not(temp) + "000000001"; elsif(arg="011") then

temp1:= temp(N-1 downto 0)&'0'; elsif(arg="100") then

temp2:= not(temp) + "000000001"; temp1:= temp2(N-1 downto 0)&'0'; else temp1:= (others=>'0'); end if; pp<= sxt(temp1, 2*N); end process; end Behavioral;

In document Design and power estimation of booth multiplier using different adder architectures (Page 39-48)