Properties of oxide dielectrics - Solution processed metal oxide microelectronics: from materia

2. Theory

2.2. Properties of oxide dielectrics

Dielectric materials play as important a role in TFTs as semiconductors and are one of the building block materials employed in electronic device

(b)

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-(a)

fabrication. Within the silicon based integrated circuit (IC) industry there is an ever increasing drive toward smaller dimension transistors, driven primarily by the search for increased circuit miniaturisation and performance [61]. This has typically been achieved through advancements in process tooling and methods. Here, thinner dielectric materials are preferable as they offer circuit miniaturisation and higher levels of capacitance per unit area, but already the IC industry is approaching the fundamental limits of materials such as SiO2. The use of new materials with high dielectric constants is now one of the strategies employed within this industry [62]. The usefulness of these materials is not only limited to the IC industry as there are a number of TFT based applications which can benefit from such materials, particularly their use in conjunction with oxide based semiconductors [63, 64]. A number of alternative oxide dielectrics with higher dielectric constants, or high-k, have already been used with oxide semiconductors. Specifically they are used due to their ability to lower the voltages at which oxide TFTs operate, and in turn lead to lower power consumption.

2.2.1 Theory of dielectrics

Dielectric materials or insulators are materials that do not transport charge, but under the application of an electrical field there is a shift in the distribution of charges within the material, or put another way they can be polarised. It is this polarisation that leads to dielectric behaviour and therefore capacitance, C [6]. If we take two electrodes distance, d, from one another and apply a voltage across them we induce an electric field given as . The charge per unit area at the electrodes is proportional to the electric field and is given as:

[2.2]

Where is the permittivity of free space. The capacitance, C is the proportionality constant between the charge and the applied voltage and is given as:

[2.3]

Once we insert a dielectric material between the two electrodes then the capacitance is increased by a factor of, k, the relative permittivity of that material. Where relative permittivity is a measure of how polarisable the material is:

[2.4]

2.2.2 Breakdown

At very high field strengths dielectrics suffer from breakdown where the material becomes highly conductive and often suffers from some form of damage beyond which the dielectric is no longer of any use. This is typically attributed charge carriers gaining significant levels of energy form the high field strength, enough so they are accelerated to a high enough velocity to ionise other atoms and free further charge carriers creating a chain reaction of events leading to very high free carrier concentration [6, 65]. The conduction band is essentially being filled with free carriers leading to an increase in material conductance.

Typically the dielectric strength is measured in megavolts per meter MV/m.

2.2.3 The dielectric/semiconductor interface

The interface between the dielectric and semiconductor within TFT devices is one of the most important factors determining device performance. Application of a gate voltage creates a charge accumulation layer at the interface, extending only a small depth into the channel, of

the order of a few nanometres thickness at maximum [66, 67]. Clearly the nature of the interface in terms of structural order, trap density etc., will have some effect on the electronic properties of such a narrow accumulation layer [67]. Roughness at the interface limits charge transport and trap states lead to shifts in threshold voltages as they require filling before charge transport can take place in the accumulation layer [68] (Fig 2.7).

Figure 2.7: Band diagram representation of metal-dielectric-semiconductor interface (a) in the case of no interfacial traps and (b) in the presence of trap states. From left to right, , flat-band condition and accumulation. The influence of the interfacial trap states leads to the pronounced shift required in to acquire the flat-band condition.

An ideal dielectric material should have a high dielectric constant, high electric field breakdown strength, a smooth and defect free surface and should be free from contaminants. Processing considerations are of course important and will depend on device application and structure. Of course we are concerned about the quality of the interface rather than just the dielectric surface alone, so we must consider the both the dielectric

Metal Dielectric Semiconductor

(a)

(b) Trap states at interface

and semiconductor a complete system rather than two individual components.

2.2.4 Trap density estimation

As discussed, traps are formed at the interface due to a distribution of states that fall below the band edge. Therefore not all carriers are available for transport and so estimation of trap densities can be useful when studying the performance of different dielectrics and comparing processing methods. Trap states can be considered as additional series capacitance and will therefore affect the TFT subthreshold slope (discussed in section 2.3) and thus we use this to ascertain the density of trap states at the interface [69]. The slope can be expressed as:

( ) [2.5]

Where is the subthreshold slope, is the additional series geometric capacitance added due to the trap states. So at room temperature with no trap states the subthreshold slope should be approximately 60mV/dec. The relation of capacitance due to trap states, to density of traps states, expressed in units of [ ][ ], is given as . So we can obtain :

(

) [2.6]

This method is not ideal as it doesn’t account for the possibility of bulk states/traps which can also affect the overall conductivity of the film and of course the subthreshold slope [70]. Alternatively we can look at the threshold voltage as it gives an indication of the number of traps that require filling before the device turns on. This is generally considered the

point of equilibrium between all trap states being filled and carriers being fully mobile. So we can estimate an areal charge trap density by the following [6]:

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[2.7]

It should be noted that as the temperature rises then the Fermi level approaches that of the band edge, therefore the number of trap states that are in need of filling for a given gate voltage will reduce. To this end it is often the case that the threshold voltage is to some degree influenced by temperature [71]. The density of trap states that are within a few kT of the band edge can be calculated as:

[2.8]

This suggests that threshold voltage is proportional to temperature, and close to the band edge the density of trap states is to some degree independent of energy. It should be noted that these methods for calculating trap densities can lead to different values as the energy systems probed in each case differ.

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