Proposed Control Technique 133

The resolution of the ADC and the DPWM blocks decide to a great extent the efficiency of the overall system. For a high resolution DPWM, a fast oscillator clock is required which

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increases the power consumption. The hypothesis is the following: fast clock and thus high resolution is only needed in the steady–state range, whereas outside that range, the clock and the resolution can be saved at low values with no effect on the performance of the system, as shown in Figure 5.1.

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Figure 5.1 illustrates the concept of irregular resolution, the output of the ADC / ,

is a fixed set of values, , depending on the resolution of the ADC and the range of the output voltage sensed.

As noticed from Figure 5.1, the resolution of the ADC during steady–state

is dictated by the minimum resolution of the output voltage determined by system requirements, with and is calculated using Equation (5.2);

2 ∆ 5.2

: is the maximum voltage at the input of the ADC divided by the number of output voltage representations 2 and this should be smaller than the minimum resolution required at the output voltage ∆ .

Using Equation (5.2), the ADC resolution during steady–state can be calculated and the resolution of the DPWM should be higher to avoid limit cycle problems.

Again, during transients the resolution of the ADC can be lowered to since the output voltage needs to be quickly relocated to the steady–state range. Either the ADC resolution or the sampling frequency can be lowered during transients. In the latter case, the resolution of the ADC can be maintained unchanged in both the steady–state and transient modes.

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The full range of the output voltage is drawn versus ADC as shown in Figure 5.1. Where, _ (minimum output voltage) corresponds to the resultant load voltage at

maximum load variation and _{_} (maximum output voltage) matches the load voltage at minimum load during step up and step down transients respectively. Also, the reference voltage is a fixed number that can be represented as a discrete value of .

The proposed control technique first distinguishes the mode of operation, steady–state or transient, and treats each case separately: if the value of the sensed output voltage lies outside the steady–state range _{_} then, a transient condition is detected and the coarse resolution ADC , which requires a slow clock, is applied during the transient to drive the output voltage back to the steady–state range as quickly as possible to alleviate the spikes that result at the load due to the transients.

Figure 5.1 also illustrates the two techniques of sampling the output voltage and assigning discrete values for each sample, i.e., if the sampled value of the output voltage lies in the range, which is outside the steady–state range, an ADC assigns to it a digitized value of . The error signal resulting from the difference is thus calculated.

Similarly, if the sampled value of the output voltage lies in the range, a discrete

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The function of the compensator is to process the errors and generate a duty cycle value such that the difference between the sensed output voltage and the reference value is zero. And accordingly a digital value of the required duty cycle is sent from the compensator to the DPWM, it is then compared to a ramp waveform and an analog duty cycle is generated that sets the output voltage equal to the reference.

Since a coarse resolution is applied during transients, the variation in duty cycle will be larger compared to the conventional regular resolution ADC.

As explained above, first; the mode of operation is to be checked. A decision needs to be taken according to the representations of the sensed value of the output voltage; if the output voltage is outside the steady–state range, a slow clock and low resolution DPWM is applied to quickly and roughly retrieve the output voltage and take it back to the steady–state range where then a fine tuning algorithm using a finer ADC with an accurately designed compensator based control loop sets the output voltage precisely at the reference value. Thus, the low resolution during transients should be able to more or less re–place the output voltage in the region of the steady–state range which is then directly followed by the steady–state fine tuning algorithm as shown in Figure 5.1.

At a zero error signal, the output voltage is equal to the desired reference value and the steady–state duty cycle at the output of the DPWM is set to a value equal to .

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Figure 5.2 Dynamically Clock–Adjusted DPWM

A fast clock and thus a high resolution DPWM is only needed during the steady–state region, whereas a slow clock and coarse resolution is sufficient outside the steady–state region. As a result, the savings in clock and consequently power loss outside the steady–state region in the proposed dynamic clock–adjusted digital ramp architecture makes it possible for converters to operate at high switching frequency with high DPWM resolution and yet improved efficiency.

The anticipated advantages reaped out of this control structure are the following:

1. During transients, a coarse sampling of the output voltage will be adequate in order to generate a duty cycle that takes the deviated output voltage back to the steady–state range.

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2. Enhanced dynamic response due to the fast recovery from load transients via the use of the coarse resolution DPWM and followed by fine tuning.

3. Reduced power consumption due to reduced clock requirement and thus a promising solution for a high switching converter.

This section is intended to present the proposed concept of dynamic clock–adjusted digital ramp architecture. This control technique is primarily addressing clocking requirements and power consumption at steady–state in addition to the dynamic response of digital converters during transients.