• Testing and modeling of bare aluminum sensing sites
• Investigation of various post-processing steps
Post-processing steps under investigation included coating the MEC with thin- layers of various dielectrics. Such coating does not require lithography, as it can be applied on the whole die surface non-selectively (as long as the bondpads are protected).
7.1 Prototype Sensor
The prototype sensor addresses the following tasks:
• Interface a biological matter with aluminum microelectrodes
• Amplify extracellular potentials
• Allow comparison of different electrode sizes
• Allow characterization of different electrode coatings
• Provides basic temperature control
The chip includes thirty differential amplification channels coupled to elec- trodes of different sizes distributed over the chip surface. Amplifiers provide gain of 40 dB sufficient to drive the signals off the chip without degrading SNR. Unity gain stages are used to drive off-chip loads. A temperature sensor for detection of 37◦ level and a special resistor for tissue heating were also included on the chip (Fig. 7.3).
x100 x1 Heating resistor Temperature sensor Channel #15 Channel #2 Channel #1 DC stabilization
Fig. 7.3.MEC blocks
7.1.1 Electrode Design
Electrodes were designed as areas of exposed top metal interconnect layer. Passivation (thick oxide, about 2.5μm width) above electrode sites was etched
84 7 MEA on Chip: In-Vitro Neuronal Interfaces
by a standard process step, similarly as it is etched above bonding pad open- ings. Conceptional chip layer stack is shown in Fig. 7.4. Process design rules demand arrays of vias placed beneath exposed top metal, to improve me- chanical stability of the bond pads. Vias contribute to the roughness of the top metal surface, degrading the quality of coating deposition. Since the elec- trodes are not bonded, one might consider removing via arrays from beneath the electrodes. We have decided to keep the vias, fearing fabrication reliabil- ity problems. Aluminum, being a non-noble metal, forms a thin (several nm)
Fig. 7.4.Layer stack in MEC
layer of oxide when introduced into a biological medium. Due to the oxide barrier, a capacitive interface is formed. For 4 nm oxide thickness and dielec- tric coefficient of 9, area capacitance of 2μF/cm2 is formed. For an electrode of 100μm2, this would be 2 pF, quite sufficient for preamplifier coupling.
As shown in [111], spontaneous oxide barrier may fail to protect aluminum electrodes from corrosion. Additional dielectric layer (Al2O3,T a2O5) can be deposited on the chip for electrode protection. Dielectric layer deposition is much less complicated than noble metal deposition, as it can be deposited over the entire chip area. Unlike noble metal, dielectric layer requires no high definition lithography and can be made with primitive mask sets for bonding pad protection. Dielectric layer, however, degrades the interface capacitance: for 40 nm deposition with dielectric constant of 20, area capacitance is only 0.44μ/cm2, 440 fF for 100μm2electrode, making amplifier design a challenge.
7.1.2 Low Noise Amplifier
Low noise preamplifier designed for NPR02 (Chap. 4) was employed for the prototype in-vitro sensor. It was found highly suitable for the in-vitro sensor due to its low input capacitance. Input capacitance of a general differential pair (Fig. 7.5) is defined by gate-source and gate-drain capacitors of the input
Coating (optional) Gate M1 M3 Mtop Passivation Substrate FieldOx M2
7.1 Prototype Sensor 85 Vd Cgs Cgd Vin (a) Vd Cgs Cgd Vin (b)
Fig. 7.5. (a) General differential pair. (b) Preamp circuit
transistor. The gate-drain capacitance exhibits Miller effect; it is effectively multiplied by the stage gain, i.e.Vd/Vin. In the preamplifier circuit, the small-
signal drain voltage of the input transistors,Vd, is effectively zero due to the
cascode transistor, thus the Miller effect is eliminated. Because of source de- generation, gate-source voltage is lower by a factor of (gmRs+1)−1, effectively
lowering the gate-source capacitor by the same factor. Input capacitance of 850fF was simulated for the preamplifier. That can be compared, for example, to the circuit used inNPR03, having input capacitance of 5 pF.
7.1.3 Input DC stabilization
DC input stabilization was achieved with periodically shortened reset gates. Although continuous bias technique was successfully used inNPR03, reset gates were adopted for simplicity of modeling and implementation. Reset gate bi- asing suffers from several serious drawbacks: Periodic artifacts are introduced into the signal because of reset pulses. While the reset gates are opened, input potentials slew slowly due to leakage currents in reset transistor diffusions. Mismatches in these leakage currents generate potential differences in elec- trodes across the chip, contributing to corrosion. Continuous bias technique would enforce constant and equal potentials over all the electrodes potentially leading to better corrosion immunity.
High-impedance input node capacitance characterization was made possi- ble by signal injection through an RC voltage divider. An array of capacitors
86 7 MEA on Chip: In-Vitro Neuronal Interfaces
of known sizes can be selectively connected to the input node, to allow several independent measurements. Since there are several unknown capacitors con- nected to the input node, several equation have to be formed to find all the unknowns. The input node with characterization circuits is shown in Fig. 7.6.
Reset
C2 C3
C1
RC voltage divider
Capacitor array
Fig. 7.6. Input node capacitance characterization