7.2.1 Chip-and-wire Assembly
Attempting to achieve multi-octave, high-efficiency operation at high power levels is significantly hampered by the reactances introduced by the package of the transistor. By shifting the optimum output impedance to a lower value, these reactive elements make the task of impedance matching more difficult, as outlined in Section 2.3.2.
One approach to overcome this limitation is to use an unpackaged, or ‘bare die’ tran- sistor in a ‘chip-and-wire’ assembly. The semiconductor wafer is sawn up into individual die, which are then attached directly to the circuit board using eutectic solder, and the gate and drain pads are wire-bonded to the transmission lines.
quality of the die attach is critical, especially for GaN devices, which dissipate a lot of heat in a relatively small area. The absence of a package also means the transistor is at greater risk to damage from its environment. Bond wires, in particular, are thin and fragile and hence are susceptible to accidental damage.
However, for the development of the third prototype amplifier, PA v3, the benefits of a chip-and-wire assembly were judged to outweigh the disadvantages, and so this approach was pursued.
7.2.2 ‘Dual-mode’ Push-Pull
During the simulation stage of the design of PA v3, it was found that the addition of output matching capacitors to ground significantly improved the high frequency perfor- mance. However, this resulted in a significant dip in performance around the centre of the amplifier’s operating bandwidth. This dip in performance can be seen in Figs. 7.1 and 7.2.
Figure 7.1: Output power of PA v3 preliminary simulations
The frequency at which the dip occurs is designated the ‘transition frequency’. In- vestigation into the time-domain waveforms revealed that at frequencies less than the transition frequency the mode of operation was similar to a non-inverted mode, as shown in the waveforms of Fig. 7.3. This is indicated by the half-wave rectified shape of the
Figure 7.2: Drain efficiency of PA v3 preliminary simulations
current waveform, and sinusoidal nature of the voltage waveform, which is flattened by a third harmonic voltage contribution. Above the critical ‘transition frequency’, the waveforms, shown in Fig. 7.4, were more similar to an inverted mode of operation. The current can be observed to be approximately sinusoidal, with the voltage resembling a half-wave rectified sinusoid. In this way, it can be observed that the PA is, in effect, working in a ‘dual mode’ of non-inverted operation below the transition frequency and inverted above it.
The harmonic voltage magnitudes at the transition frequency are greatly increased compared to the rest of the band, resulting in the highly irregular waveforms of Fig. 7.5 and reduced output power and efficiency. The variation in fundamental and harmonic voltage magnitudes with frequency is shown in Fig. 7.6.
Figure 7.3: Simulated time-domain waveforms below the transition frequency This is a highly interesting phenomenon, however it should be noted that it would be necessary to build a prototype amplifier with the transition frequency deliberately included to verify that this dip in performance could be observed through measurement.
Figure 7.4: Simulated time-domain waveforms above the transition frequency
Figure 7.5: Simulated time-domain waveforms at the transition frequency
It is possible that this dip is related to the one observed in the measured results of PA v2, although this cannot be determined at present.
If the ‘dual mode’ is discovered to be present in prototype amplifiers, this suggests that frequency-dependent biasing should be investigated, as the biasing requirements differ for inverted and non-inverted modes of operation. Analysis of the waveforms should be able to provide information on the optimum condition for each frequency. It is unlikely that one bias point is optimum for all frequencies, especially over the bandwidths being considered in this thesis.
7.2.3 Design and Simulated Results
It was decided that, as with the first two prototype designs, good performance at all frequencies across the band would be targeted, as opposed to a ‘dual-band’ design with a dip in performance at the transition frequency. Efforts were made to eliminate the dip in performance without removing the output matching capacitors and hence compromising the performance across the rest of the bandwidth. The best performance was obtained by implementing a ‘virtual ground’ between the two halves of the amplifier, where the output matching capacitors were connected together via an area of copper microstrip which was not grounded. Interestingly, this was also required for the input matching capacitors, and further investigation is needed to establish why this is. The final layout is shown in Fig. 7.7, and the simulated performance compared to the second prototype amplifier is shown in Figs. 7.8 and 7.9.
Figure 7.8: Comparison of simulated output power for PA v2 and PA v3
Figure 7.9: Comparison of simulated drain efficiency for PA v2 and PA v3 It can be seen in Fig. 7.8 that the output power is similar to PA v2 across most of the band, which is to be expected, but that it is improved at higher frequencies. However, the drain efficiency, shown in Fig. 7.9, is significantly improved across almost all of the bandwidth. This is a very promising result, and shows the potential perfor- mance improvements of the chip-and-wire approach combined with appropriate output matching. It should be noted that this is simulated data, however it is hoped that the improved performance in simulation will be realised in practice and reflected in the measured results.