Radiation Hardened Processing Architectures

Dedicated radiation hardened processes are used to manufacture processors capable of enduring the harsh radiation environments. These architectures can have multiple qualities such as their radiation effects resilience and sometimes these processors can achieve high performance. This can be reached when a custom design technique is used, identical to the design of COTS high performance; such as the PowerPC architecture, resulting in a painless code compatibility and application to the space domain. This method will provide high-level incorporation, including special I/O controllers, especially for the space domain. In this section we will introduce some radiation hardened processing architectures, showing the different hardware mitigation techniques used against the SEEs and the complexity of their

150 circuits.

A.4.1 Using PCM in Next-generation Embedded Space Applications

Radiation hardened DRAM for embedded systems dedicated to space applications is a necessity because of the imminent thread of gamma rays, causing transient errors. However, such rad-hard memories are costly, and have higher power consumption, leading to lower battery life, or an increase in weight, for circuits designed for space applications.

A new memory technology has emerged recently [193], named the phase-change memory (PCM), which has a great potential because of its low power consumption, non-volatility, scalability, and radiation mitigation. All the mentioned positive characteristics of PCM make it the ideal candidate to replace DRAM for space applications, requiring radiation immunity. On the other hand, current approaches necessitate changes to PCM device’s internal circuitry, the OS and/or CPU cache memory configuration/interface.

Phase Change Main Memory Architecture (PMMA) presents a new architecture to manage the use of PCM. It was designed avoiding alterations to commodity PCM circuitry, the OS, and the CPU cache memory interface. This will allow plug-in change of a traditional DRAM main memory by one built with PMMA. PMMA combine creative scheme to handle PCM’s constraints, including write operations delays, asymmetric read/write overhead, and poor endurance. This work shows that PMMA improves the energy-delay by 60% over conventional DRAM main memories.

The architecture of the Memory Manager (MM) is depicted in Figure A-1. It incorporates a request controller, a request buffer, an In-Flight Buffer (IFB), a PCM controller and an Acceleration and Endurance Buffer (AEB) DRAM controller. The request controller allocates resources for CPU interface requests and executes the memory transactions on behalf of the CPU. It is the element that controls the AEB and the PCM devices while revealing the same memory interface to the CPU. The request buffer upholds information about awaiting requests. It saves the current state of a request, including the request’s CPU/DRAM/PCM addresses, size of the package and the resources used to manage the request (e.g., buffers and tag array entries). The request controller uses the In-Flight Buffer, a short-term data storage. In order to read/write data from the DRAM and PCM devices, The PCM and AEB controllers are equipped with DMA engines.

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Figure A-1 PCM Memory Management Internal Architecture [37]

Reference [194] suggests that in order to overcome the Flash memories scaling limits, PCM can be used to replace the Floating Gate (FG) Flash memories.

In the last years, several solutions have been explored in order to overcome the Flash memories scaling limits. Phase Change Memories (PCM) [194]seem to be one of the most promising candidates to replace FG Flash memories.

A.4.2 Quad-Core Radiation-Hardened System-on-Chip

The RAD55xX™ system-on-chip platform (SoC) IC is designed based on QorlQ [195] from Freescale [196], with further special qualities for the space domain. RAD55xX™ can be customized depending on the need. The RAD55xx has a quad-core 32/64 bit Power Architecture [197] processors, three levels of cache, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high-speed links. The RAD55xx [198] uses radiation-hardened by design RH45™ technology [199], by optimizing power and performance.

Figure A-2 illustrates the RAD5545™ microprocessor architecture, which contains dual interleaved DDR3 ports, to compensate the delay resulted from cache misses. The CCBR interfaces are powered off, as they are internal.

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Figure A-2 RAD5545 Quad-Core Microprocessor Personality Block Diagram

A.4.3 SCS750 Architecture

The SCS750 [200] was manufactured to have high radiation tolerance, without neglecting the performance aspects. The block diagram of the board is shown in Figure A-3, including the fault tolerance technologies in each block. This architecture can have more than 1800 MIPS, using the PowerPC 750FX [201], a processing architecture with 800MHz frequency, 32 Kbytes instruction and 32 Kbytes data on-chip L1 cache and 512 Kbytes on-chip L2 cache, 256 Mbytes of Reed-Solomon protected SDRAM, 4 Mbytes of EEPROM with FEC.

153 A.4.4 Honeywell's RHPPC Integrated Circuit

The RHPPC Processor [202] is fabricated on a 0.35 µm SIMOX CMOS process, including four metal levels, designed Radiation hardened CMOS V (RICMOS-V), considered as a cell ASIC architecture with personalized “drop-in” designs for the caches, tag memory management unit, and register files. The smallest transistor gate dimensions are 0.35 µm length by 0.8 µm width. In order to determine the ion energy loss in SEE testing, an active silicon layer depth of 0.2 µm, and another surface layer of 8 µm above it are used. The RHPPC Processor is manufactured on an HX311P die model and built in a 255 pin ceramic ball grid array (BGA) package. In this work, the current RHPPC Processor version denoted as “Pass2a” has been assessed. This architecture saves more power with slightly improved SEU mitigation, compared to the early “Pass2” version. The RHPPC Processor functionality is similar to the commercial PowerPC 603e™ microprocessor [203]. The following design modifications enable the RHPPC Processor to mitigate the SEEs:

• In order to avoid transfer gates wire-ORed to a single node with a keeper, the tristate multiplexer was removed.

• The associated precharge logic was cancelled by substituting the dynamic adder as a static adder.

• The implementation of a radiation hard phase-locked loop (PLL) custom cell, including extra inputs and two status outputs (IN_LOCK and LOCK_DETECT outputs).

• The clock regeneration cell is customized for radiation tolerance.

Additional radiation-hardening was achieved by replacing the Honeywell’s SEU-hardened latch, register, and memory for similar functionalities in a commercial device. The result is a 3.6 million transistor architecture with 146,000 HX3000-series standard SEU-hardened cells and 10 custom SEU- hardened drop-in arrays. A block diagram of RHPPC processor is presented in Figure A-4.

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Figure A-4 RHPPC Processor Functional Block Diagram