Refresh Requirements

Table 101: Refresh Requirement Parameters (Per Density)

Parameter Symbol 4Gb 6Gb 8Gb 16Gb 32Gb Unit

Number of banks – 8 TBD

Refresh window: T_CASE ≤ 85˚ t_{REFW 32 TBD ms}

Refresh window: 1/2 rate t_{REFW 16 TBD ms}

Refresh window: 1/4 rate t_{REFW 8 TBD ms}

Required number of REFRESH commands (MIN)

R 8192 TBD

Average time between REFRESH commands (for reference only) T_CASE ≤ 85˚C

REFab t_{REFI 3.9 TBD μs}

REFpb t_{REFIpb 0.4875 TBD μs}

Refresh cycle time t_{RFCab 130 210 TBD TBD ns}

AC Timing

Table 102: AC Timing

Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

Maximum frequency – – 667 800 933 1066 MHz

Clock Timing

Average clock period t_{CK(avg) MIN 1.5 1.25 1.071 0.938 ns}

MAX 100

Average HIGH pulse width t_{CH(avg) MIN 0.45} t_CK(avg)

MAX 0.55

Average LOW pulse width t_{CL(avg) MIN 0.45} t_CK(avg)

MAX 0.55

Absolute clock period t_{CK(abs) MIN} t_{CK(avg) MIN +} t_{JIT(per) MIN ns}

Absolute clock HIGH pulse width

t_{CH(abs) MIN 0.43} t_CK(avg)

MAX 0.57

Absolute clock LOW pulse width

t_{CL(abs) MIN 0.43} t_CK(avg)

MAX 0.57

Clock period jitter (with sup- ported jitter)

t_{JIT(per), al-}

lowed

MIN –80 –70 -60 -50 ps

MAX 80 70 60 50

Maximum clock jitter be- tween two consecutive clock cycles (with allowed jitter)

t_{JIT(cc), al-}

lowed

MAX 160 140 120 100 ps

Duty cycle jitter (with sup- ported jitter)

t_JIT(duty),

allowed

MIN min((t_{CH(abs),min -} t_{CH(avg),min),}

(t_{CL(abs),min -} t_{CL(avg),min)) ×} t_CK(avg)

ps MAX max((t_{CH(abs),max -} t_{CH(avg),max),}

(t_{CL(abs),max -} t_{CL(avg),max)) ×} t_CK(avg)

Cumulative errors across 2 cy- cles

t_ERR(2per),

allowed

MIN –118 –103 -88 -74 ps

MAX 118 103 88 74

Cumulative errors across 3 cy- cles

t_ERR(3per),

allowed

MIN –140 –122 -105 -87 ps

MAX 140 122 105 87

Cumulative errors across 4 cy- cles

t_ERR(4per),

allowed

MIN –155 –136 -117 -97 ps

MAX 155 136 117 97

Cumulative errors across 5 cy- cles

t_ERR(5per),

allowed

MIN –168 –147 -126 -105 ps

MAX 168 147 126 105

Cumulative errors across 6 cy- cles

t_ERR(6per),

allowed

MIN –177 –155 -133 -111 ps

MAX 177 155 133 111

Cumulative errors across 7 cy- cles

t_ERR(7per),

allowed

MIN –186 –163 -139 -116 ps

MAX 186 163 139 116

Cumulative errors across 8 cy- cles

t_ERR(8per),

allowed

MIN –193 –169 -145 -121 ps

Table 102: AC Timing (Continued) Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

Cumulative errors across 9 cy- cles

t_ERR(9per),

allowed

MIN –200 –175 -150 -125 ps

MAX 200 175 150 125

Cumulative errors across 10 cycles

t_ERR(10per),

allowed

MIN –205 –180 -154 -128 ps

MAX 205 180 154 128

Cumulative errors across 11 cycles

t_ERR(11per),

allowed

MIN –210 –184 -158 -132 ps

MAX 210 184 158 132

Cumulative errors across 12 cycles

t_ERR(12per),

allowed

MIN –215 –188 -161 -134 ps

MAX 215 188 161 134

Cumulative errors across n = 13, 14, 15…, 19, 20 cycles

t_ERR(nper),

allowed

MIN t_{ERR(nper),allowed MIN = (1 + 0.68ln(n)) ×} t_{JIT(per), allowed MIN}

ps MAX t_{ERR (nper), allowed MAX = (1 + 0.68ln(n)) ×}

t_{JIT(per), allowed MAX}

ZQ Calibration Parameters

Initialization calibration time t_{ZQINIT MIN 1 μs}

Long calibration time t_{ZQCL MIN 360 ns}

Short calibration time t_{ZQCS MIN 90 ns}

Calibration RESET time t_{ZQRESET MIN MAX (50ns, 3nCK) ns}

READ Parameters4

DQS output access time from CK

t_{DQSCK MIN 2500 ps}

MAX 5500

DQSCK delta short t_{DQSCKDS MAX 265 220 190 165 ps 5}

DQSCK delta medium t_{DQSCKDM MAX 593 511 435 380 ps 6}

DQSCK delta long t_{DQSCKDL MAX 733 614 525 460 ps 7}

DQS-DQ skew t_{DQSQ MAX 165 135 115 100 ps}

DQS output HIGH pulse width

t_{QSH MIN} t_{CH(abs) - 0.05} t_CK(avg)

DQS output LOW pulse width

t_{QSL MIN} t_{CL(abs) - 0.05} t_CK(avg)

DQ/DQS output hold time from DQS

t_{QH MIN MIN (}t_QSH, t_{QSL) ps}

READ preamble t_{RPRE MIN 0.9} t_{CK(avg) 8, 9}

READ postamble t_{RPST MIN 0.3} t_{CK(avg) 8, 10}

DQS Low-Z from clock t_{LZ(DQS) MIN} t_{DQSCK (MIN) - 300 ps 8}

DQ Low-Z from clock t_{LZ(DQ) MIN} t_{DQSCK (MIN) - 300 ps 8}

DQS High-Z from clock t_{HZ(DQS) MAX} t_{DQSCK (MAX) - 100 ps 8}

DQ High-Z from clock t_{HZ(DQ) MAX} t_{DQSCK (MAX) + (1.4 ×} t_{DQSQ (MAX)) ps 8}

Table 102: AC Timing (Continued) Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

DQ and DM input hold time (VREF based)

t_{DH MIN 175 150 130 115 ps}

DQ and DM input setup time (V_REF based)

t_{DS MIN 175 150 130 115 ps}

DQ and DM input pulse width

t_{DIPW MIN 0.35} t_CK(avg)

Write command to first DQS latching transition

t_{DQSS MIN 0.75} t_CK(avg)

MAX 1.25

DQS input high-level width t_{DQSH MIN 0.4} t_CK(avg)

DQS input low-level width t_{DQSL MIN 0.4} t_CK(avg)

DQS rising edge to CK falling edge and DQS falling edge to CK rising edge setup time

t_{DSS MIN 0.2} t_CK(avg)

CK rising edge to DQS falling edge and CK falling edge to DQS rising edge hold time

t_{DSH MIN 0.2} t_CK(avg)

Write postamble t_{WPST MIN 0.4} t_CK(avg)

Write preamble t_{WPRE MIN 0.8} t_CK(avg)

CKE Input Parameters CKE minimum pulse width (HIGH and LOW pulse width)

t_{CKE MIN MAX (7.5ns, 3nCK)} t_CK(avg)

CKE input setup time t_{ISCKE MIN 0.25} t_{CK(avg) 11}

CKE input hold time t_{IHCKE MIN 0.25} t_{CK(avg) 12}

Command path disable delay t_{CPDED MIN 2} t_CK(avg)

Command Address Input Parameters4 Address and control input

setup time

t_{ISCA MIN 175 150 130 115 ps 13}

Address and control input hold time

t_{IHCA MIN 175 150 130 115 ps 13}

CS_n input setup time t_{ISCS MIN 290 270 230 205 ps 13}

CS_n input hold time t_{IHCS MIN 290 270 230 205 ps 13}

Address and control input pulse width

t_{IPWCA MIN 0.35} t_CK(avg)

CS_n input pulse width t_{IPWCS MIN 0.7} t_CK(avg)

Boot Parameters (10–55 MHz)14, 15, 16

Clock cycle time t_{CKb MAX 100 ns}

MIN 18

CKE input setup time t_{ISCKEb MIN 2.5 ns}

Table 102: AC Timing (Continued) Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

Address and control input setup time

t_{ISb MIN 1150 ps}

Address and control input hold time

t_{IHb MIN 1150 ps}

DQS output data access time from CK

t_{DQSCKb MIN 2 ns}

MAX 10

Data strobe edge to output data edge

t_{DQSQb MAX 1.2 ns}

Mode Register Parameters MODE REGISTER WRITE com- mand period (MRW com- mand to MRW command in- terval)

t_{MRW MIN 10} t_CK(avg)

MODE REGISTER SET com- mand delay (MRW command to non-MRW command inter- val)

t_{MRD MIN MAX (14nx, 10nCK) ns}

MODE REGISTER READ com- mand period

t_{MRR MIN 4} t_CK(avg)

Additional time after t_{XP has}

expired until MRR command may be issued

t_{MRRI MIN} t_{RCD (MIN) ns}

Core Parameters17

READ latency RL MIN 10 12 14 16 t_CK(avg)

WRITE latency (set A) WL MIN 6 6 8 8 t_CK(avg)

WRITE latency (set B) WL MIN 8 9 11 13 t_CK(avg)

ACTIVATE-to- ACTIVATE com- mand period

t_{RC MIN} t_{RAS +} t_{RPab (with all-bank precharge)} t_{RAS +} t_{RPpb (with per-bank precharge)}

ns CKE minimum pulse width

during SELF REFRESH (low pulse width during SELF RE- FRESH)

t_{CKESR MIN MAX (15ns, 3nCK) ns}

SELF REFRESH exit to next valid command delay

t_{XSR MIN MAX (}t_{RFCab + 10ns, 2nCK) ns}

Exit power-down to next val- id command delay

t_{XP MIN MAX (7.5ns, 2nCK) ns}

CAS-to-CAS delay t_{CCD MIN 4} t_CK(avg)

Internal READ to PRE- CHARGE command delay

t_{RTP MIN MAX (7.5ns, 4nCK) ns}

Table 102: AC Timing (Continued) Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

Row precharge time (single bank)

t_{RPpb MIN MAX (18ns, 3nCK) ns}

Row precharge time (all banks)

t_{RPpab MIN MAX (21ns, 3nCK) ns}

Row active time t_{RAS MIN MAX (42ns, 3nCK) ns}

MAX 70 μs

WRITE recovery time t_{WR MIN MAX (15ns, 3nCK) ns}

Internal WRITE-to- READ command delay

t_{WTR MIN MAX (7.5ns, 4nCK) ns}

Active bank A to active bank B

t_{RRD MIN MAX (10ns, 2nCK) ns}

Four-bank ACTIVATE window t_{FAW MIN MAX (50ns, 8nCK) ns}

Minimum deep power-down time

t_{DPD MIN 500 μs}

ODT Parameters

Asynchronous RTT turn-on de-

ly from ODT input

t_{ODTon MIN 1.75 ns}

MAX 3.5

Asynchronous RTT turn-off

delay from ODT input

t_{ODToff MIN 1.75 ns}

MAX 3.5

Automatic RTT turn-on delay

after READ data

t_{AODTon MAX} t_{DQSCK + 1.4 ×} t_{DQSQmax +} t_{CK(avg,min) ps}

Automatic R_TT turn-off delay after READ data

t_{AODToff MIN} t_{DQSCKmin - 300 ps}

RTT disable delay from pow-

er-down, self refresh, and deep power-down entry

t_{ODTd MAX 12 ns}

R_TT enable delay from pow- er-down and self refresh exit

t_{ODTe MAX 12 ns}

CA Training Parameters First CA calibration command following CA training entry

t_{CAMRD MIN 20} t_CK(avg)

First CA calibration command following CKE LOW

t_{CAENT MIN 10} t_CK(avg)

CA calibration exit command following CKE HIGH

t_{CAEXT MIN 10} t_CK(avg)

CKE LOW following CA cali- bration mode entry

t_{CACKEL MIN 10} t_CK(avg)

CKE HIGH following last CA calibration results

Table 102: AC Timing (Continued) Notes 1–3 apply to all parameters and conditions

Parameter Symbol Min/Max Data Rate

Unit Notes

1333 1600 1866 2133

Data out delay after CA training calibration com- mand entry t_{ADR MAX 20 ns} MRW CA exit command to DQ tri-state t_{MRZ MIN 3 ns} CA calibration command to CA calibration command de- lay

t_{CACD MIN RU(}t_ADR/t_{CK) + 2} t_CK(avg)

Write Leveling Parameters DQS delay after write level- ing mode is programmed

t_{WLDQSEN MIN 25 ns}

MAX –

First DQS edge after write leveling mode is program- med

t_{WLMRD MIN 40 ns}

MAX –

Write leveling output delay t_{WLO MIN 0 ns}

MAX 20

Write leveling hold time t_{WLH MIN 205 175 150 135 ps}

Write leveling setup time t_{WLS MIN 205 175 150 135 ps}

Temperature Derating Parameters DQS output access time from

CK (derated)

t_{DQSCK MAX 5620 ps}

RAS-to-CAS delay (derated) t_{RCD MIN} t_{RCD + 1.875 ns}

ACTIVATE-to- ACTIVATE com- mand period (derated)

t_{RC MIN} t_{RC + 1.875 ns}

Row active time (derated) t_{RAS MIN} t_{RAS + 1.875 ns}

Row precharge time (derat- ed)

t_{RP MIN} t_{RP + 1.875 ns}

Active bank A to active bank B (derated)

t_{RRD MIN} t_{RRD + 1.875 ns}

Notes: 1. Frequency values are for reference only. Clock cycle time (t_{CK) is used to determine de-}

vice capabilities.

2. All AC timings assume an input slew rate of 2 V/ns.

3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX. 4. READ, WRITE, and input setup and hold values are referenced to VREF.

5. t_{DQSCKDS is the absolute value of the difference between any two} t_{DQSCK measure-}

ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.

t_{DQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is}

<10˚C/s. Values do not include clock jitter.

6. t_{DQSCKDM is the absolute value of the difference between any two} t_{DQSCK measure-}

guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include clock jitter.

7. t_{DQSCKDL is the absolute value of the difference between any two} t_{DQSCK measure-}

ments (in a byte lane) within a 32ms rolling window. t_{DQSCKDL is not tested and is}

guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include clock jitter.

8. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in

the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for t_RPST, t_{HZ(DQS) and} t_{HZ(DQ)), or begins driving (for} t_RPRE, t_{LZ(DQS) and} t_{LZ(DQ)). The figure below shows a method to calculate the point when}

the device is no longer driving t_{HZ(DQS) and} t_{HZ(DQ) or begins driving} t_{LZ(DQS) and} t_{LZ(DQ) by measuring the signal at two different voltages. The actual voltage measure-}

ment points are not critical as long as the calculation is consistent. The parameters

t_LZ(DQS), t_LZ(DQ), t_{HZ(DQS), and} t_{HZ(DQ) are defined as single-ended. The timing pa-}

rameters t_{RPRE and} t_{RPST are determined from the differential signal DQS.}

Output Transition Timing

V_OL + 2x X mV V_OL + X mV V_OH - X mV V_OH - 2x X mV 2x X X 2x Y V_OH V_OL Y T1 T2 V_TT - Y mV V_TT V_TT V_TT - 2x Y mV V_TT + 2x Y mV V_TT + Y mV _{tLZ(DQS), tLZ(DQ)} tHZ(DQS), tHZ(DQ) T1 T2

Start driving point = 2 × T1 - T2 End driving point = 2 × T1 - T2

actual wave f_o

rm

9. Measured from the point when DQS begins driving the signal, to the point when DQS begins driving the first rising strobe edge.

10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driv- ing the signal.

11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK crossing.

12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltage level.

13. Input setup/hold time for signal (CA[9:0], CS_n).

14. To ensure device operation before the device is configured, a number of AC boot timing parameters are defined in this table. Boot parameter symbols have the letter b appen- ded (for example, t_{CK during boot is} t_CKb).

15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET (MRW) command, as specified in Mode Register Definition.

16. The output skew parameters are measured with default output impedance settings us- ing the reference load.

In document CS0_n 1K A[9:0] 2K A[10:0] addressing/cs_n (Page 138-146)