Reset Cause (RESC), offset 0x05C

This field specifies the cause of the reset event to software. The reset value is determined by the cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are cleared. However, if the reset is due to any other cause, the remaining bits are sticky, allowing software to see all causes.

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed.

0 EXT R/W - When set to 1, an external reset (RST assertion) is the cause of the reset event.

reserved

WDT BOR POR EXT

SW LDO

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Register 17: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed.

Bit/Field Name Type Reset Description

31:28 Reserved RO 0 Reserved bits return an indeterminate value, and should never be changed.

27 ACG R/W 0 Auto Clock Gating

This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers (see page 90) and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers (see page 90) if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode.

Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers (see page 90) are used when the controller enters a sleep mode.

The RCGCn registers are always used to control the clocks in Run mode.

This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused.

RO 0

Run-Mode Clock Configuration (RCC)

Offset 0x060

reserved ACG USESYSDIV USEPWMDIV PWMDIV

OEN XTAL IOSCVER MOSCVER IOSCDIS MOSCDIS

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26:23 SYSDIV R/W 0xF System Clock Divisor

Specifies which divisor is used to generate the system clock from the PLL output (200 MHz).

When reading the Run-Mode Clock Configuration (RCC) register (see page 84), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used.

This lower value is allowed to divide a non-PLL source.

22 USESYSDIV R/W 0 Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source.

21 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed.

20 USEPWMDIV R/W 0 Use the PWM clock divider as the source for the PWM clock.

Bit/Field Name Type Reset Description

Binary Value

Divisor (BYPASS=1)

Frequency (BYPASS=0) 0000 reserved reserved

0001 /2 reserved

0010 /3 reserved

0011 /4 reserved

0100 /5 reserved

0101 /6 reserved

0110 /7 reserved

0111 /8 25 MHz

1000 /9 22.22 MHz

1001 /10 20 MHz

1010 /11 18.18 MHz

1011 /12 16.67 MHz

1100 /13 15.38 MHz

1101 /14 14.29 MHz

1110 /15 13.33 MHz

1111 /16 12.5 MHz (default)

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19:17 PWMDIV R/W 0x7 PWM Unit Clock Divisor

This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock.

16:14 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed.

13 PWRDN R/W 1 PLL Power Down

This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. See Table 6-4 on page 88 for PLL mode control.

12 OEN R/W 1 PLL Output Enable

This bit specifies whether the PLL output driver is enabled.

If cleared, the driver transmits the PLL clock to the output.

Otherwise, the PLL clock does not oscillate outside the PLL module.

Note: Both PWRDN and OEN must be cleared to run the PLL.

11 BYPASS R/W 1 PLL Bypass

Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider.

Note: The ADC module must be clocked from the PLL or directly from a 14-MHz to an 18-MHz clock source in order to operate properly.

Bit/Field Name Type Reset Description

Value Divisor

10 PLLVER R/W 0 PLL Verification

This bit controls the PLL verification timer function. If set, the verification timer is enabled and an interrupt is generated if the PLL becomes inoperative. Otherwise, the verification timer is not enabled.

9:6 XTAL R/W 0xB This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided in Table 6-4 on page 88.

Oscillator-Related Bits

5:4 OSCSRC R/W 0x0 Picks among the four input sources for the OSC. The values are:

3 IOSCVER R/W 0 This bit controls the internal oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative.

Otherwise, the verification timer is not enabled.

2 MOSCVER R/W 0 This bit controls the main oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative.

Otherwise, the verification timer is not enabled.

1 IOSCDIS R/W 0 Internal Oscillator Disable

0: Internal oscillator is enabled.

1: Internal oscillator is disabled.

0 MOSCDIS R/W 0 Main Oscillator Disable

0: Main oscillator is enabled.

1: Main oscillator is disabled.

Table 6-3. PLL Mode Control

PWRDN OEN Mode

1 X Power down

0 0 Normal

Bit/Field Name Type Reset Description

Value Input Source

00 Main oscillator (default) 01 Internal oscillator

10 Internal oscillator / 4 (this is necessary if used as input to PLL)

11 reserved

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Table 6-4. Default Crystal Field Values and PLL Programming Crystal Number

(XTAL Binary Value) Crystal Frequency (MHz)

0000-0011 reserved

0100 3.579545 MHz

0101 3.6864 MHz

0110 4 MHz

0111 4.096 MHz

1000 4.9152 MHz

1001 5 MHz

1010 5.12 MHz

1011 6 MHz (reset value)

1100 6.144 MHz

1101 7.3728 MHz

1110 8 MHz

1111 8.192 MHz

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