5.2 Modified-ACO (MACO) for Logic Design
5.3.3 Residual Function
Given suitable time to evolve, the proposed algorithm could find the target truth table. However, it could happen that after a given maximum number of iterations, functionally correct circuits are not produced. In this case, two approaches can be used, either to have another run of the algorithm, or to extend the search by using current solution as initial state for the heuristic. No modifications are needed to perform the first approach. The second approach requires some modifications so that the extension of the search is performed intelligently. This section addresses the approach used for extending the search in ELD.
Extending the Search
The goal of ELD is to produce functional and optimized circuits. A solution whose functional fitness is 0.9 is not considered as a good solution. However, in terms of evolution process, it is 90% functional. Given the time to evolve, it is hoped that by extending the search into a more directed solution space, the fully functional circuits can emerge from this solution.
Consider, for example, the target truth table (F ) for the algorithm to be gener- ated is 10010011. Assume that after maximum iteration is reached, the best solution returned by the algorithm has the truth table (f1) 10010000. The functional fitness of the solution is ‘only’ 0.75. Assume that the searching process is continued by targeting residual truth table (f2) 00000011. Then, if f2 is obtained, both f1 and
f2 can be merged using an OR gate to build the intended truth table F . Since the search space for f2 is likely to be smaller than the search space for F , the possibility to find f2 is greater compared to F .
The residual function f2 is obtained by decomposing function F to f1 OR f2. The decomposition procedure in Boolean algebra allows the use of don’t care values (*). Thus, the truth table of f2 will be *00*0011. The don’t care values will allow us to explore richer solution space. In addition to that, the target solutions will increase, since there are four representations for f2: 00000011, 00010011, 10000011, and 10010011. This makes the searching process more promising. The procedure of
how the decomposition is performed is discussed below.
Decomposition Rules
Decomposition plays an important part in the conventional logic design algorithms. The idea is to divide a Boolean function into some lower complexity sub-functions, so that the overall representation can be minimized. Decomposition can be formulated as follows. Given F as a Boolean function, find f1,...,fk so that F = G(f1, ..., fk),
where G is a Boolean operator (a gate). The sub-functions f1 or fk can be decom-
posed further to obtain simpler functions.
Decomposition can be performed in many ways. Since only two inputs gate are used, there are three types of decomposition considered, namely: OR, AND and XOR decomposition. These names denote the gate used for the decomposition. Thus, decomposition process can be formulated as follows.
Given Boolean function F and known sub-function f1
AND decomposition : f ind f2 so that F = f1· f2
OR decomposition : f ind f2 so that F = f1+ f2
XOR decomposition : f ind f2 so that F = f1⊕ f2
Unfortunately, not all functions can be decomposed using AND or OR decompo- sition. There is a need of a procedure to check whether a function is decomposable by AND (OR) decomposition or not. Table 5.2 and Table 5.3 show the value of
Table 5.2: AND decomposition table. F f1 f2 Meaning Coding 0 0 * don’t care 2 0 1 0 logic 0 0 1 0 - can’t happen 3 1 1 1 logic 1 1
f2 for different input pattern of F and f1 for AND and OR decomposition, respec- tively. If the value of f2 is ‘-’ (can’t happen condition), then the function F is not decomposable using f1.
Table 5.3: OR decomposition table.
F f1 f2 Meaning Coding
0 0 0 logic 0 0
0 1 - can’t happen 3
1 0 1 logic 1 1
1 1 * don’t care 2
In contrast with the AND and OR decomposition, function f2 can always be produced by decomposing F to f1 by XOR decomposition, since f2 = F ⊕ f1. However, in XOR decomposition, the f2 will be in the form of completely specified functions, i.e., the truth table of f2 does not have don’t cares values, as shown in Table 5.4. Thus, it is possible that f2 is more complex than f1 (or F ) itself.
Merging the solutions
Using the concept of residual function, the algorithm will work in at least two stages. The first stage is to find f1, while the second one is to find f2. At the end of the second stage, f1 and f2 will be merged to obtain a new solution. Consider,
Table 5.4: XOR decomposition table. F f1 f2 Meaning Coding 0 0 0 logic 0 0 0 1 1 logic 1 1 1 0 1 logic 1 1 1 1 0 logic 0 0
for example, a function F with truth table 1000111111100101. Assume that the first stage of the algorithm found f1 whose truth table is 0000111110100101 (see Figure 5.15 (a)). Assume that OR decomposition is used. Using OR decomposition table, truth table of f2 is then 1000*****1*00*0*. Assumed that the second stage of the algorithm find f2 with truth table 1000001001000001, shown in Figure 5.15 (b). With OR gate as operator, the function F0 obtained from merging f1and f2is shown
in Figure 5.15 (c).
If F0 = F , it means that the algorithm found the functionally correct circuits.
However, it is possible that f2 was not found and F0 6= F . In this case, another
stage of decomposition must be performed. The new f2 will be calculated by using
F0 as f
1. This process is continued until the maximum number of decomposition
d a' b' d' a c' b (a) (b) d' a c' d a' b' b F 1 f 2 f (c) merging decomposition operator
Decomposition() If (s = 0) and (solution.F F = 1) Return solution Else If (s > 0) Merge(f1, f2, G, F0) If (F0 = F ) Return solution EndIf f1 ← solution If (s = 0) G = OR gate ElseIf (s = 1) G = AND gate Else
If Check decompose(F , f1, OR) > 0
G = OR gate
ElseIf Check decompose(F , f1, AND) > 0
G = AND gate
Else G = XOR gate EndIf
Decompose(F , f1, G, f2) EndIf
stages allowed is reached.
In order to get the benefit of the don’t care values, both of AND and OR decom- position get higher priority compared to the XOR decomposition. The justification is that the unneeded minterms from f1 can be removed using AND decomposition and the required minterms can be added using the OR decomposition. Note that the “can’t happen” condition will be treated as normal don’t cares. If both decomposi- tions fail, the XOR decomposition is performed. Figure 5.16 shows the pseudocode of decomposition procedure.
Improved Modified ACO (IMACO) algorithm /* MAXITER Maximum iteration */
/* MAXSTAGE Maximum decomposition stage */ For 0 < s < MAXST AGE
For 0 < i < MAXIT ER Filling the Matrix(); Ant Activity();
Removing Unfit Cells(); Perturbation();
End
Decomposition(); End
Return best solution End
Putting It All Together
Having the perturbation and decomposition procedures incorporated, the improved modified ACO (IMACO) algorithm for logic design is presented in Figure 5.17.
The IMACO algorithm is more complex compared to the previous one (see Fig- ure 5.5). However, the probability of obtaining better quality result is higher. Ex- perimental results and comparison between the proposed algorithms will be given in the next chapter.
5.4
Concluding Remarks
In this chapter, a Modified Ant Colony Optimization (MACO) algorithm for the design of digital logic circuits is introduced. The need for a modification to the original ACO algorithm is discussed. Moreover, an improved version of the MACO algorithm that includes the use of perturbation and residual function is also pro- posed. In the next chapter, performance evaluation, experiments and results of the proposed algorithm are presented.
EXPERIMENTS AND RESULTS
This chapter and the following one are dedicated to experiments and results obtained from applying the proposed algorithms. This chapter concentrates on the evaluation of different possible schemes, while the next chapter will present comparison with existing techniques.6.1
Experimental Setup
A number of procedures needed for conducting the experiments are first introduced. This includes the setting of inputs, tools and parameters.
Input: In order to perform the experiments, some benchmark circuits are used as test cases. The benchmark consists of twenty randomly generated truth tables of different complexity in addition to twelve circuits obtained from ISCAS’85 bench-
mark. All circuits are in PLA format. Using this format, the proposed algorithm can accept don’t care inputs as mentioned in Section 3.4. Details of these circuits are given in Appendix A. Table 6.1 shows a summary of these circuits.
Table 6.1: Summary of circuits used for the experiments.
Single Output Multiple Output
Circuits
Number of
Specification Number of Specification Notes used
circuits circuits
Random 20 Number of - - -
inputs: 2 - 6
Number of Number of arithmetic circuits:
inputs: 3 - 7 inputs: 3-7 majority, parity,
ISCAS’85 3 9
Number of adder and multiplier outputs: 2-10
Technology parameters used in the experiments is obtained from MOSIS 0.25 µ library [80]. These parameters are written into a text file using a certain format. This can be seen in Appendix A.
Parameters for the Algorithm: Performance of iterative heuristics depends on the fine-tuning of its parameters. Otherwise mentioned explicitly, in general, these parameters listed below are used. Note that NV is the number of variables for a specific circuit. • α = 1 • β = 1 • ρ = 0.1 • Number of ants = 10 * NV • Number of generations = 2 * NV
• Number of runs = 20
• Minimum size of the matrix = NV × NV
• Maximum size of the matrix = (k1 · NV ) × (k2· NV ), 2 ≤ k2 < k1
• Maximum number of decomposition stages = 6
Four types of experiments are carried out to measure the performance of the proposed algorithms. These include experiments for different fitness function calcu- lation, effect of dynamic search space, effect of perturbation and decomposition, and different optimization objectives. The quality of solutions are measured according to the area, delay and power of the circuits. These metrics are measured in µm2, ps and pW units, respectively.