SHR instruction shifts the bits in op1 to right by the number of times specified by op2 .
Example:( 1 ) Example:( 1 )
SHR
SHR BP, BP, 1 1 ; ; Shift Shift word word in in BP BP by by 1 1 bit bit position position to to right right and and 0 0 is is kept kept toto MSB
MSB
Example:( 2 ) Example:( 2 )
MOV
MOV CL, CL, 03H 03H ;Load ;Load desired desired number number of of shifts shifts into into CLCL SHR
SHR BYTE BYTE PYR[BX] PYR[BX] ;Shift ;Shift bytes bytes in in DS DS at at offset offset BX BX and and rotate rotate 3 3 bits bits to to rightright and keep 3 0’s in MSB and keep 3 0’s in MSB Example:( 3 ) Example:( 3 ) ;SI = 10010011 10101101 , CF = 0 ;SI = 10010011 10101101 , CF = 0 SHR
SHR SI, SI, 1 1 ; ; Result: Result: SI SI = = 01001001 01001001 11010110 11010110 and and CF CF = = 1, 1, OF OF = = 1, 1, SF SF == 0, ZF = 0
0, ZF = 0
SAR Instruction - Shift operand bits right, new MAB = old MSBSAR Instruction - Shift operand bits right, new MAB = old MSB
SAR instruction shifts the bits in the operand specified by op1 towards right by count SAR instruction shifts the bits in the operand specified by op1 towards right by count specified in op2.As bit is shifted out a copy of old MSB is taken in MSB. MSB position specified in op2.As bit is shifted out a copy of old MSB is taken in MSB. MSB position and LSB is shifted to CF.
and LSB is shifted to CF.
Syntax - SAR destination, count. Syntax - SAR destination, count.
Example: ( 1 ) Example: ( 1 )
; AL = 00011101 = +29 decimal, CF = 0 ; AL = 00011101 = +29 decimal, CF = 0 SAR
SAR AL, AL, 1 1 ;Shift ;Shift signed signed byte byte in in AL AL towards towards right right ( ( divide divide by by 2 2 )) ;AL = 00001110 = + 14 decimal, CF = 1 ;AL = 00001110 = + 14 decimal, CF = 1 Example: ( 2 ) Example: ( 2 ) ;BH = 11110011 = - 13 decimal, CF = 1 ;BH = 11110011 = - 13 decimal, CF = 1 SAR
SAR BH, BH, 1 1 ;Shifted ;Shifted signed signed byte byte in in BH BH to to right right and and BH BH = = 11111001 11111001 = = - - 77 decimal, CF = 1.
decimal, CF = 1.
ROTATE INSTRUCTIONS
ROTATE INSTRUCTIONS
ROL Instruction - Rotate all bits of operand left, ROL Instruction - Rotate all bits of operand left, MSB to LSBMSB to LSB
ROL instruction rotates the bits in the operand specified by oper1 towards left by the ROL instruction rotates the bits in the operand specified by oper1 towards left by the count specified in oper2. ROL moves each bit in the operand to next higher bit position. count specified in oper2. ROL moves each bit in the operand to next higher bit position. The higher order bit is moved to lower order position. Last bit rotated is copied into carry The higher order bit is moved to lower order position. Last bit rotated is copied into carry flag.
Example: ( 1 ) Example: ( 1 )
ROL
ROL AX, AX, 1 1 ;Word ;Word in in AX AX is is moved moved to to left left by by 1 1 bit bit and and MSB MSB bit bit is is to to LSB, LSB, andand CF and CF =0 ,BH =10101110
CF and CF =0 ,BH =10101110 ROL
ROL BH, BH, 1 1 ;Result: ;Result: CF CF ,Of ,Of =1 =1 , , BH BH = = 0101110101011101
Example : ( 2 ) Example : ( 2 )
;BX = 01011100 11010011 and CL = 8 bits to rotate ;BX = 01011100 11010011 and CL = 8 bits to rotate ROL
ROL BH, BH, CL CL ;Rotate ;Rotate BX BX 8 8 bits bits towards towards left left and and CF CF =0, =0, BX BX =11010011=11010011 01011100
01011100
ROR Instruction - Rotate all bits of opROR Instruction - Rotate all bits of operand right, LSB to MSBerand right, LSB to MSB
ROR instruction rotates the bits in the operand oper1 to wards right by count specified in ROR instruction rotates the bits in the operand oper1 to wards right by count specified in op2. The last bit rotated is copied into CF.
op2. The last bit rotated is copied into CF. Syntax - ROR destination, count
Syntax - ROR destination, count
Example:( 1 ) Example:( 1 )
ROR
ROR BL, BL, 1 1 ;Rotate ;Rotate all all bits bits in in BL BL towards towards right right by by 1 1 bit bit position, position, LSB LSB bit bit isis moved to MSB and CF has last rotated bit.
moved to MSB and CF has last rotated bit.
Example:( 2 ) Example:( 2 )
;CF =0, BX = 00111011 01110101 ;CF =0, BX = 00111011 01110101 ROR
ROR BX, BX, 1 1 ;Rotate ;Rotate all all bits bits of of BX BX of of 1 1 bit bit position position towards towards right right and and CF CF =1,=1, BX = 10011101 10111010 BX = 10011101 10111010 Example ( 3 ) Example ( 3 ) ;CF = 0, AL = 10110011, ;CF = 0, AL = 10110011, MOVE
MOVE CL, CL, 04H 04H ; ; Load Load CLCL ROR
ROR AL, AL, CL CL ;Rotate ;Rotate all all bits bits of of AL AL towtowards ards right right by by 4 4 bits, bits, CF CF = = 0 0 ,AL ,AL == 00111011
00111011
RCL Instruction - Rotate operand around to the left through CFRCL Instruction - Rotate operand around to the left through CF
RCL instruction rotates the bits in the operand specified by oper1 towards left by the RCL instruction rotates the bits in the operand specified by oper1 towards left by the count specified in oper2.The operation is circular, the MSB of operand is rotated into a count specified in oper2.The operation is circular, the MSB of operand is rotated into a carry flag and the bit in the CF is rotated around into the LSB of operand.
carry flag and the bit in the CF is rotated around into the LSB of operand. Syntax - RCL destination, source.
Syntax - RCL destination, source.
Example(1): Example(1):
CLC
CLC ;put ;put 0 0 in in CFCF RCL
RCL AX, AX, 1 1 ;save ;save higher-order higher-order bit bit of of AX AX in in CFCF RCL
RCL DX, DX, 1 1 ;save ;save higher-order higher-order bit bit of of DX DX in in CFCF ADC
ADC AX, AX, 0 0 ; ; set set lower lower order order bit bit if if needed.needed.
Example (2): Example (2):
RCL
RCL DX, DX, 1 1 ;Word ;Word in in DX DX of of 1 1 bit bit is is moved moved to to left, left, and and MSB MSB of of word word is is given given toto CF and CF to LSB CF=0, BH = 10110011
CF and CF to LSB CF=0, BH = 10110011 RCL
RCL BH, BH, 1 1 ;Result ;Result : : BH BH =01100110 =01100110 CF CF = = 1, 1, OF OF = = 1 1 because because MSB MSB changed changed CFCF =1,AX =00011111 10101001
=1,AX =00011111 10101001 MOV
MOV CL, CL, 2 2 ;Load ;Load CL CL for for rotating rotating 2 2 bit bit positionposition RCL
RCL AX, AX, CL CL ;Result: ;Result: CF CF =0, =0, OF OF undefined undefined AX AX = = 01111110 01111110 1010011010100110
RCR Instruction - Rotate operand around to the right through CFRCR Instruction - Rotate operand around to the right through CF
RCR Instruction - RCR instruction rotates the bits in the operand specified by operand1 RCR Instruction - RCR instruction rotates the bits in the operand specified by operand1 towards right by the count specified in operand2.
towards right by the count specified in operand2. Syntax - RCR destination, count
Syntax - RCR destination, count
Example:(1) Example:(1)
RCR
RCR BX, BX, 1 1 ;Word in ;Word in BX BX is is rotated rotated by by 1 1 bit bit towards towards right right and and CF CF will will containcontain MSB bit and LSB contain CF bit .
MSB bit and LSB contain CF bit .
Example:(2) Example:(2)
;CF = 1, BL = 00111000 ;CF = 1, BL = 00111000 RCR
RCR BL, BL, 1 1 ;Result: ;Result: BL BL = = 10011100, 10011100, CF CF =0 =0 OF OF = = 1 1 because because MSB MSB is is changed changed toto 1.
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Definition:
Definition: The meaning of ‘interrupts’ is to break the sequence of operation.While theThe meaning of ‘interrupts’ is to break the sequence of operation.While the cpu is executing a program,on ‘interrupt’ breaks the normal sequence of execution of cpu is executing a program,on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main
(ISR).After executing ISR , the control is transferred back again to the main program.Interrupt processing is an alternative to polling.
program.Interrupt processing is an alternative to polling.
Need for Interrupt:
Types of Interrupts:
Types of Interrupts:There are two types of Interrupts in 8086. They are:There are two types of Interrupts in 8086. They are: (i)
(i)Hardware InterruptsHardware Interrupts andand (ii)
(ii)Software InterruptsSoftware Interrupts (i) Hardware Interrupts
(i) Hardware Interrupts(External Interrupts). The Intel microprocessors(External Interrupts). The Intel microprocessors supportsupport hardware interrupts
hardware interruptsthrough:through:
Two pins that allow interrupt requests, INTR and NMITwo pins that allow interrupt requests, INTR and NMI
One pin that acknowledges, INTA, the interrupt requested on INTR.One pin that acknowledges, INTA, the interrupt requested on INTR. INTR and NMI
INTR and NMI
INTRINTR is a maskable hardware interrupt. The interrupt can be enabled/disabledis a maskable hardware interrupt. The interrupt can be enabled/disabled
using STI/CLI instructions or using more complicated method of updating the using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction.
FLAGS register with the help of the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack,When an interrupt occurs, the processor stores FLAGS register into stack,
disables further interrupts, fetches from the bus one byte representing interrupt disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction.
IRET instruction.
NMINMI is a non-maskable interrupt. Interrupt is processed in the same way as theis a non-maskable interrupt. Interrupt is processed in the same way as the
INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority processing routine is stored in location 0008h. This interrupt has higher priority than the maskable interrupt.
than the maskable interrupt.
–– Ex: NMI, INTR.Ex: NMI, INTR. (ii) Software Interrupts
(ii) Software Interrupts (Internal Interrupts and Instructions) .S(Internal Interrupts and Instructions) .Software interroftware interrupts canupts can be caused by:
be caused by:
INT instruction - breakpoint interrupt. This is a type 3 interrupt.INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256INT <interrupt number> instruction - any one interrupt from available 256
interrupts. interrupts.
INTO instruction - interrupt on overflowINTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt.Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt.
When the CPU processes this interrupt it clears TF flag before calling the When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.
interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and EscapeProcessor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape
opcode (type 7). opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts.Software interrupt processing is the same as for the hardware interrupts.
-- Ex: INT nEx: INT n (Software Instructions)(Software Instructions)
Control is providedControl is provided through:through:
o
o IF and TF flag bitsIF and TF flag bits o