SABER Simulation Verification of Control Loop

The results of the MATLAB control analysis were verified with a SABER simulation. The control block, in Figure 6-18, consists of the converter output feedback attenuator, and an extra operational amplifier acting as a buffer to avoid loading the resistor chain, the non linear relay with voltage dead band, the PI voltage compensator, a saw tooth waveform generator, the PWM stage comparator and a gate drive interface. The feedback attenuator reduces Vbus by

a factor of 100. Regulation dead band limits Vhigh and Vlow are set by ideal voltage sources of

-5.6 V and – 6.4 V respectively. A fixed 60 kHz saw tooth waveform is generated by an LM555 timer and fed to the PWM stage comparator to be compared with the output of the PI compensator.

The following simulations demonstrate the dynamic performance of the DCM buck- boost converter with the proposed voltage regulation band control. The results presented are

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all for a nominal input voltage Vs=230 Vrms with the output power, Pout, varying in a stepped

manner. Ideal operational amplifiers were used in the simulation, thus there is no offset voltage at the input of the PI compensator to introduce a positive or negative drift in K, hence making D vary and Vbus drift between voltage limits.

Figure 6-18 SABER simulation schematic of control loop and PFC converter

The following plots, Figure 6-19 to Figure 6-21, show the converter control loop response being subjected to a step load change of 0 W to 60 W, 0 W to 120 W and 0 W to 180 W. At 80.0 ms there is no load across the output capacitor, C1, and K is low to prevent

MOSFET switching and charging of C1. At 0.1 s the step load occurs, causing the voltage

across C1 to reduce. The control loop does not respond until Vbus reaches the upper voltage

limit, - 560 V. The capacitor C1 is the only source of energy to the load before the upper

voltage limit is reached. The control loop only regulates Vbus when the -560 V limit is

exceeded, as is seen by an increase in K at around 0.11 s. The response of K in these figures is such that it does not overcompensate Vbus, due to the 90ο phase margin, forcing it towards the

lower voltage boundary, -640 V, where the control loop again would have to correct, causing further oscillations.

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Figure 6-19 SABER Vbus response to step load 0 W to 60 W

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Figure 6-21 SABER Vbus response to step load 0 W to 180 W

During the step load change, Vbus repeatedly becomes more positive than limit Vhigh for

a number of cycles despite the PI compensator attempting to regulate Vbus back within the

voltage regulation band. The maximum output voltage of the compensator, K, is limited by zener diode D5, and a high frequency oscillation can be seen during the cross over of Vbus at

around 0.11 s as K increases and the natural 100 Hz ripple of Vbus attempts to pull the voltage

beyond the regulation band. This high frequency oscillation can be eliminated by reducing the gain of the PI compensator, which will in turn reduce the band width of the open loop stage. However, reducing the PI compensator gain would cause Vbus to sag significantly during step

load increases, and the subsequent constant current power stages to operate beyond their specifications.

For this application step load changes would only occur at the turn on of the LED constant current regulators. Other step load conditions to which the application may be subject are those when the LED string is required to dim or brighten. Figure 6-22 details the converter subject to a change in load from 0 W to 60 W with step load increases to 120 W and finally 180 W at 10 ms, 0.1 s and 0.3 s respectively. Figure 6-23 shows the converter subject to a change of load from 0 W to 180 W followed by step load decreases to 120 W and 60 W, at 5 ms, 0.1 s and 0.3 s.

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Figure 6-22 SABER Vbus response to step load from 0 W to 60 W to 120 W to 180 W

Figure 6-23 SABER Vbus response to step load from 0 W to 180 W to 120 W to 60 W

From these simulations it can be seen that the simulated model of the power stage and its control loop are performing as expected and are suitable for this application.

6.10 Summary

This chapter has presented a thorough analysis of a modified regulation band voltage controller for a HP LED power factor correction converter. Due to the implications of the performance characteristics of the PFC stage, a suitable control loop had to be realised that

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whose operation would regulate the PFC output voltage, but would not generate any significant input current harmonics. A modified regulation band controller detailed in Chapter 1 is developed that fulfils this criterion.

A detailed description of operation of this method is discussed and the dynamics of the control loop are analysed. Due to the non linearity presented by the regulation band, Circle Criterion is applied to determine the system loop stability whilst MATLAB and SABER simulations validate the initial theoretical analysis. Finally a discrete regulation band controller is designed for implementation in a proof of concept prototype.

An important contribution of this chapter is the development, analysis and design of a control approach that has not been presented in any literature for this application. This work forms part of a conference paper and presentation at the IEEE Power Electronics, Machines and Drives, 2008, York.

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