90-95, 43-36 SD15-0 I/O Host data bus.

Pin 31

SMEMRB -Host memory read command.

Pin 32

SMEMWB-Host memory write command. This pin is added to decode the write

command of a flash memory.

Memory Interface Pins (including BROM, EEPROM)

Pin75

BCSB-BROM chip select. Active low signal, asserted whenBROM is read. RTL8019AS

drives this pin low whenSA19-14 matches the selected BROM memory baseaddress and either of the 2 conditions below meets:

(1) SMEMRB is low

(2) SMEMWB is low and RTL8019AS's flash memory write function is enabled.

Pin 76

EECS-9346 chip select. Active high signal, asserted when 9346 is read/write.

Pin 66-69, 71-74

BA21-14 -BROM address.*

Pin 77-82, 84-85

Pin 79

EESK-9346 serial data clock.

Pin 78

EEDI -9346 serial data input

Pin 77

EEDO- 9346 serial data output.The following pins are defined for jumper options. Their

states are latched at the falling edge of RSTDRV, then they are changed to serve as the SRAM bus. Each of them is internally pulled down by a 100KW resistor. Therefore, the input will be low when left open and high when pulled up by a 10K resistor externally.

Pin 66

PNP- When it is high in jumperless mode (i.e. JP=low), the RTL8019AS is forced into

Plug and Play mode regardless of the contents of 9346.

The following pins are don't care in jumperless mode(JP=low).

Pin 72-71, 69-67

[BS4-0] -Select BROM size and base address.

Pin 85-84, 82-81

[IOS3-0]- Select I/O base address.

Pin 77, 74

[PL1-0]-Select network medium type. Pin 80-78

[IRQS2-0]-Select one interrupt line among INT7-0.

Pin 65

JP -When high, this pin selects jumper mode. When low, it selects jumperless modes

(including RT jumperless and Plug and Play).

AUI -This input is used to detect the usage of an external MAU on the AUI interface. The

input should be driven low for embedded BNC and high for external MAU. When the input is high, RTL8019AS sets the AUI bit (bit5) in CONFIG0 and drives LEDBNC low to disable the BNC. If this pin is not used, it should be connected to GND such that RTL8019AS acts like RTL8019.

Pin 54,53

CD+,CD- This AUI collision input pair carries the differential collision input signal from

the MAU.

Pin 56,55

RX+,RX- This AUI receive input pair carries the differential receive input signal from

the MAU.

Pin 49,48

TX+,TX- This AUI transmit output pair contains differential line drivers which send

Manchester encoded data to the MAU. These outputs are source followers and require 270 ohm pulldown resistors to GND.

Pin 59,58

TPIN+,TPIN- This TP input pair receives the 10 Mbits/s differential Manchester

encoded data from the twisted-pair wire.

Pin 45,46 TPOUT+,

TPOUT-This pair carries the differential TP transmit output. The output Manchester

encoded signals have been pre-distorted to prevent overcharge on the twisted-pair media and thus reduce jitter.

Pin 50

X1-20Mhz crystal or external oscillator input. Pin 51

LED Output Pins

Pin 60

LEDBNC-This pin goes high when RTL8019AS's medium type is set to 10Base2 mode

or auto-detect mode with link test failure. Otherwise, this pin is low. This pin can be used to control the power of the DC convertor for CX MAU and connected to an LED to indicate the used medium type.

Pin 61

LED0- When LEDS0 bit (in CONFIG3 register of RTL8019AS Page3) is 0, this pin acts

as LED_COL. When LEDS0=1, it acts as LED_LINK.

Pins 62,63

LED1,LED2-When LEDS1 bit (in CONFIG3 register of RTL8019AS Page3) is 0, these

2 pins act as LED_RX & LED_TX respectively. When LEDS1=1, these pins act as LED_CRS & MCSB. Please refer to section 6.5 for details of the lightening behavior of all LEDs.

REGISTERS

RTL includes4 pages of registers which are selected by bit PS0 & PS1 in the CR register.Each page contains 16 registers.

The RTL is controlled through an array of on-chip registers. Its registers are used during initialization, packet transmission and reception. There are also registers for Remote DMA operations on the. Basically, using its internal registers we can perform the same logical operations. The basic operations include defining the hardware physical address, setting the receive parameters and setting the transmission parameters. For the RTL, add configuring DMA channels and allocating transmit and receive Buffer Ring areas to the aforementioned list of operations. In that DMA is an integral part of the RTL8019AS’s microcontroller interface,there must be a control mechanism or register to act as the traffic cop for the data flow between the RTL’s buffers and the microcontroller memory and the RTL8019AS’s MAC engine to Ethernet interface. That control register for the RTL8019AS is the Command Register (CR), which is used to initiate Remote DMA operations as well as data transmission. Remember, Remote DMA operations are used to move data between the RTL buffer and the microcontroller’s memory.

The microcontroller checks for a valid frame by polling an interrupt pin (INT0) on

the RTL8019AS. Once a valid level is sensed on the INT0 pin, the micro controller interrogates the RTL Interrupt Status Register (ISR) to determine what type of interrupt has occurred.

RTL transmit packets in accordance with the CSMA/CD protocol standards. It schedule retransmission of packets up to 15 times on collisions according to the truncated binary exponential backoff algorithm. Once you cut the transmit process loose, both Ethernet ICs run the show until the transmission cycle is aborted or completed.

Assuming buffer memory is allocated and free; transmitting packets with the RTL entails setting up an IEEE 802.3 frame in memory with Ethernet frame of 6 bytes of the destination address (DA),6 bytes of the source address (SA), data length in bytes

and data.Once the required frame items are built in the microcontroller’s packet array memory area, the RTL register TPSR (Transmit Page Start Register) represents the upper byte of a 16-bit address and is

loaded with the frame starting address and the TBCR0 (Transmit Byte Count 0) and TBCR1 (Transmit Byte Count 1) registers are filled with the length of the frame.

TPSR Register

7 6 5 4 3 2 1 0

A15 A14 A13 A12 A11 A10 A9 A8

TBCR0 Register 7 6 5 4 3 2 1 0 TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 TBCR1 Register 7 6 5 4 3 2 1 0 TBC15 TBC14 TBC13 TBC12 TBC11 TBC10 TBC9 TBC8

To initiate the transmission of a packet, the TXP (transmit packet) bit of the RTL Command Register is set. If the total length of the Ethernet packet is less than 46 bytes, the RTL cannot be instructed to automatically pad the packet to avoid sending a runt packet onto the network. Therefore, we must as programmers make sure we don’t generate any runt packets. The TCP/IP section checks for runts. The ARP, ICMP and UDP routines use the length of the incoming packets as their guide. Since we will setup the RTL8019AS to not accept runt packets, the UDP and ICMP packets received will always meet the minimum length requirement. The ARP code builds a 60-byte ARP reply packet.

The RTL transmit buffer area is allocated according to the contents of its register. The RTL datasheet stresses that if the Buffer Ring area of the RTL is set up correctly at initialization, there should never be any contention for transmit buffer memory under normal operating conditions. It uses its Local DMA channel and FIFO to follow the RTL-generated preamble with valid data. The RTL Local DMA bursts data to the FIFO, which is then serialized out onto the network as clocked NRZ data.

Every Ethernet IC on a network has to conform to these standards in order to communicate with each other. The RTL Local DMA refreshes the FIFO when the FIFO “send more” threshold is reached.

The FIFO “send more” threshold is programmable. It continues the transmission as long as the transmission byte count in the byte count registers is greater than zero. Once all bytes are sent, the CRC is calculated by and is sent to complete the packet.

If a collision occurs during transmission, the transmission is stopped and 32 ones (a jam sequence) are transmitted to make sure everybody on the network segment knows a collision just took place RTL execute the Standard Back off algorithm and the transmission is retried. When the transmission completes RTL have transmit status registers(TSR) that can be queried to see how the transmission went.

TSR Register

we’re working with a bunch of standards that allow differing Ethernet IC manufacturers to design and build products that can communicate with each other over a common medium called Ethernet. Now with that in mind, transmitting data and receiving data from the ether is a process where RTL listen to the wire sense a carrier and start syncing up with the alternating 1/0 preamble that starts a 10 Mbps Ethernet

packet.Once the two consecutive ones of the SFD (Start of Frame Delimiter) are sensed, the preamble ends and the MAC engines within the RTL expect everything behind the set of SFD ones to be valid data.It checks the destination address (DA) to see if the incoming packet is addressed to them. If it is not, it is not moved into buffer memory and the packet is discarded. On the other hand, if the packet destination address matches the Ethernet

IC’s address filter setting (hashed or individual), then the frame is moved into the Ethernet IC’s on-chip buffer memory so it can be

transferred to the microcontroller’s RAM (Random Access Memory) for processing. If everything goes OK during the receive cycle, it posts receive status in their respective receive status registers and raises an interrupt I/O line.

The data coming into the RTL from the network is put into a receive Buffer Ring;

The RTL ring buffer is a classic circular, head and tail buffer scheme with

four pointers(PSTSRT,PSTOP,CURR,BNRY) controlling the activity in the Buffer Ring

A graphical representation of the RTL8019AS Buffer Ring

Although the buffer pointers can hold a 64K value (0xFFFF), note that only 8K of buffer RAM is available in the RTL8019AS.

PSTART (Page Start) is the beginning address of the Buffer Ring. PSTOP (Page Stop) is

the address of the end of the Buffer Ring. The Buffer Ring size is determined by the number of bytes between PSTART and PSTOP.

PSTART and PSTOP are loaded at initialization time.

CURR, the Current Page Pointer, points to the next available buffer area for the next incoming frame.

BNRY, or the Boundary Pointer, points to the next frame to be unloadedfrom the Buffer Ring. CURR as the write pointer and the BNRY as the read pointer for the Buffer Ring.

As frames come in, the CURR pointer moves ahead of the BNRY pointer around the ring. If CURR reaches BNRY, the Buffer Ring is full. All receptions are aborted, and missed packet registers within the RTL8019AS are updated until this condition is cleared. The RTL Remote DMA channel is the mechanism that removes frames from the Buffer Ring.

Representation of an initialized Buffering. An empty ring is signaled by the CURR and BNRY pointers being equal.

Each Realtek RTL8019AS ring buffer segment in Figure above is 256 bytes in length. A

valid received frame is placed at location CURR plus a 4-byte offset. Buffer segments are

automatically linked together to receive frames larger than 256 bytes. When all the bytes are loaded, the RSR (Receive Status Register) status, a pointer to the next frame and the byte count of the current

RealtekRTL8019AS and any other NE2000-compatible Ethernet IC works.

A visual of a frame inside the RTL8019AS’s Buffer Ring is shown in Figure