The second photolithography mask is then used to create the precise and delicate features in the central transistor region. This is shown as the two

tracks in the center of the mask in Figure 5.11d. The region that will end up as the polysilicon gate is covered by an opaque region of the mask during photolithography. However, the thin channels that correspond to the source 188

5.9 Layout Rules 189

and drain are exposed, and in those regions the photoresist is selectively damaged and removed. Etching then removes the polysilicon from the top surface of these "naked" regions. Figure S.lld shows the wafer at this stage:

the polysilicon is etched away except for the small central gate region.

Step 13: This next step is an important one: phosphorus or arsenic, n-type materials, are ion-implanted into these "naked" regions of the originally p-type wafer/substrate. A diffusion process is then used to drive in the phosphorus to create the highly doped n+regions. The transistor is now defined. The two n+channels in Figure 5.1Od are the source and the drain. They are straddled by the polysilicon gate.

Step 14: Let's pause again. The important work is now finished purely from the point of view of building the transistor itself. The remainder of the steps that follow are more concerned with creating the interconnections and pro-tecting the surface.

Step 15: A further CVD oxidation step covers the wafer shown at the top left of Figure S.l1e. Then, the third mask is used to open up the contact areas to the source, gate, and drain. This third mask is shown on the right of Figure 5.11e. The contact openings for the n+regions are the four small squares on each side of the gate lines.

Step 16: The surface of the wafer is then metallized with aluminum. Sputtering or evaporation is used for this step.

Step 17: A fourth mask shown on the bottom right of Figure 5.11 is used to create the pattern of interconnections to the other transistor circuits. The shaded areas of Figure 5.11e show the cross-sectional views of the aluminum contacts.

Step 18: The remainder of the metal not needed for the interconnections is etched away.

Step 19: A passivation layer of CVD oxide is deposited on the wafer.

Step 20: Small windows for bonding pads are opened up at the periphery of the Ie.

Thin wires are connected to these bonding pads. In later operations, during the back-end processing (Section 5.11), these are connected to the lead frame of the package. Final cleaning and passivation create the final I'C ready for such back-end packaging.

5.9 LAYOUT RULES

As in the mechanical world of Chapters 3 and 4, the design of the transistor layout is constrained by the physics of manufacturing. Design rules are required to account for variations in mask alignment, depth of focus problems in lithography, etching, and lateral diffusion. The main constraint is the minimum mask dimension that can, with fidelity, be transferred to a wafer. Design rules specify the minimum horizontal tntralayer spacings between features on the same layer. Other design rules govern

, ..

Semiconductor Manufacturing Chap. 5 theinterlayer transistor layouts between layers. The dimensions of the contacts, vias, and wells are also governed by rules.

Distances in the figures that follow are measured in ascalable design length, X, following a general procedure" proposedbyMead and Conway (1980). In fact, these scalable design lengths do not scale in an entirely linear manner, and they err on the conservative side. As a result, today's industries tend to use the micron rules. which directly prescribe preferred dimensions. Nevertheless, for an introductory text such as this, the Mead and Conway scalable ideas are presented because they are generic.

5.9.1Intralayer Design Rules

In the first Figure 5.13, the active transistor areas are 3A.in dimension and 3). apart.

The polysilicon gate region is 2A.The metal regions are typically 3A.The contacts through to the active transistors and the metal-to-metal via holes are 2A. CMOS wells are larger at lOA.

5.9.2Interlayer Design Rules

Figure 5.14a shows a polysilicon layer(po)overlapping and defining the channel on an n+diffusion region. It means that the minimum length of the active transistor will be 2A-as defined by the minimum width of polysilicon in the previous Figure 5.13.

The minimum width will be 3A-as defined by the minimum width of diffusion to create an active region. The dimension from the active region to the well boundary is SA.Note that such design rules specify minimum distances from a "feature to an

4In the current MOSIS system the minimum line width is set to 2A. For example, for a 1.2 micron process (i.e., a process with a minimum line width of 1.2 microns),A =0.6 micron.

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-3-FlgmeS.13 Minimum dimensions and spacings of intralayer design rules (nom DigUtlllntegrated Circuits by Rabaey, © 1996. Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, NJ)

5.9 Layout Rules 191

Transistor ~

Metal-to-poly (b)

FIpre 5.14 lnterlayer rules (from Digitallnttgrah!dCircuits by Rabaey,Q1996.

Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, Nl).

edge." This is the same concept used in Figure 4,17, where in the mechanical CAD/CAM system, the minimum distance from a "feature to an edge" is specified, In Figure 5.14b. the design rules for the vertical openings that allow aluminum to penetrate down to the active transistor are specified, along with the dimensions of the vertical vias that interconnect different metal layers. For example, the label

"metal-to-active" on the left of the diagram is next to a darkened 2 X 2 square that represents a vertical opening that allows the connection between the m1 aluminum and the n+active transistor site. Figure 5.15 shows a combined view of a simple device. It includes (a) layout, (b) cross section. and (c) circuit diagram.

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192 Semiconductor Manufacturing Chap, 5

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Figure 5.15 Example layout including the vertical process cross section and corresponding circuit diagram (from DigimllnlegratedCircuits by Rabaey, © 1996.

Reprinted by permission of Prentice-Hall, Inc.,Upper Saddle River, NJ).

5.10 MORE DETAILS ON FRONT-END PROCESSING

A variety of excellent texts present comprehensive details of the front-end processes: Mueller and Kamins (1986), Jaeger (1988), Pierret (1996), and Campbell (1996). Some key aspects are summarized in the next few pages.

5.10.1Silicon Ingots and Waf.r Preparation

The process beginsbyheating relatively low grade silicon, or ferrostlicon, with carbon in an electric furnace. A series of reduction steps creates impure silicon. Con-version to liquid silicon chloride allows purificationbydistillation. Heating SiC4 in a hydrogen atmosphere creates ultrapure polyerystalline silicon.

00' GND

5.10 More Details on Front-End Processing 19.

A single crystal silicon ingot is next produced by the Czochralski method of unidirectional casting. A solid siliconseed finger is dipped into the vat of molten, ultrapure silicon and then slowly withdrawn (Figure 5.16). When growing the single crystal, the solidification direction is usually aligned to the <111> or the <100>

direction. This causes the molten silicon to cool as a single crystal around the finger and be drawn out into a long cylinder of the required diameter.

This polycrystalline silicon ingot can be ground to a uniform smoothness and polished. It is then sliced with a diamond saw into circular wafers about 0.5 mm thick and 200 or 300 nun in diameter. The wafer surfaces are also ground and polished.

Wafers are chemically cleaned to remove all traces of particles, bacteria, and other impurities. The procedure involves dipping a rack of wafers into successive boiling chemical and deionized water baths. This is an extremely toxic and hazardous process requiring extensive safety and environmental protection measures.

5.10.2Thermal Oxidation Procedures

As described already, the starting sequence for a typical MOS process is to grow a thin padding of silicon dioxide onto the wafer. Wafers are heated in furnaces and exposed to purified oxygen under carefully controlled conditions as shown in Figure 5.17a.

In later processing steps for the thicker field oxide, the wafers can be heated in a water vapor atmosphere. The water vapor method shown in Figure 5.17b builds layers more quickly than dry oxygen heating.

Seed

FIpre5.16 Simplified Czochrabki method for unidirectional solidification.

Seed shaft Seed holder

Silica crucible Graphite crucible

[

Crucible shaft

In document 21st Century Manufacturing - P. Wright (2002) WW (Page 195-200)