Security in Emerging Technologies based Computing Systems

With CMOS technology scaling down to deep nanometer realm, process variation has become more and more pronounced. The increasing process variations lead to consider-able uncertainty in circuit performance and large spread in chip speed. The imprecision provided by the deeply downscaled nanometer CMOS technology no longer holds on the widely accepted practice of designing circuits that operate on deterministic zeros and ones. One interesting direction is to exploit the inherent randomness for cryptographic purposes. A broad objective is to embed security and cryptographic primitives into customized circuits with negligible overhead by making use of the inherent randomness.

For example, in the sub-threshold or near-threshold applications, soft errors can be di-rectly used as PUF response and/or random numbers. The advantage is manifest in the fact that this approach does not incur any overhead, since these soft errors are cre-ated by voltage over-scaling for the low-power purpose that will be corrected by certain compensation algorithm at a later stage.

At meanwhile, as the semiconductor industry contemplates the end of Moore’s Law, there has been a groundswell of interest in technologies that offer a path to scale beyond the limits of the current CMOS technology. Emerging technologies that might help ex-tend the life of Moore’s Law, such as carbon nanotubes [123], nanowire arrays [124], and molecular FETs [125], present both challenges and opportunities for digital cir-cuit design. Most of these technologies are characterized by very high defect rates, as well as large amounts of inherent randomness. For example, it is nearly impossible to guarantee perfect alignment and accurate positioning of all carbon nanotubes at VLSI scale. Mispositioned and misaligned carbon nanotubes can result in incorrect digital logic functionality. Hardware security of emerging technologies can be a very important research topic in the future. For example, future non-volatile memory systems, such

as phase change memory (PCM), spin torque transfer magnetoresistive RAM (STT-MRAM), and resistive RAM (RRAM), typically have large number of intrinsic defects.

A non-volatile storage system includes solutions to mask intrinsic defects, read and era-sure endurance and cell coupling problems. When used appropriately, such information allows unique identification of non-volatile memory. Different technologies might to be considered within an overall framework for security applications. Future work can be directed towards developing a general method to inherently extract randomness on non-volatile memory systems for security signature or random number applications.

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