Verification of today’s multi-million gate ASIC designs requires speed that in most cases cannot be provided using software-based simulation. ASIC emulation or prototyping on an FPGA-based platform is a cost-effective option available to design and verification engineers. It can speed up your software-based simulation exponentially, which will improve coverage and decrease the overall time-to-market availability of the product. Another role of prototyping is to provide a pre-silicon platform for early system integration of the design for firmware and applications software.
Selecting an emulation or prototyping platform that is capable of accelerating ASIC design verification is a complex process that can take you a long time before you make the final decision. The process includes a thorough evaluation of existing platforms and making sure that all of the technical and budgetary requirements like emulation capacity, speed, cost, coverage, and tool support are met.
One of the platform evaluation goals is to uncover any hidden issues and perform a feasibility analysis. FPGA-based platforms are more restrictive than the ones based on custom processors. Some ASIC designs might have a fundamental problem of being partitioned, synthesized, or implemented for a specific FPGA-based platform.
Nomenclature
There is no consistent terminology that defines the different kinds of hardware acceleration platforms. Terms like emulation, prototyping, co-emulation, co-simulation, and in-circuit emulation are often used interchangeably, and the difference is not always clear.
There are several differences between emulation and prototyping platforms. Emulation platforms provide better debuggin capabilities close to the ones available in software simulators. That allows you to use emulation platforms in a wider range of project phases: from the block-level simulation to full-chip ICE (In-Circuit Emulation) and debug. Emulation platforms offer a more integrated solution such as a push-button build and debug flows, and more sophisticated software tools. Prototyping platforms lack good debug visibility, and are typically used during pre-silicon system integration and software debug. A prototyping platform might be a simple bare bones board with rudimentary software tools. The performance, or the emulation speed, of a prototyping platform is better: tens of MHz comparing to a few MHz in the emulation platform. Emulation platforms are usually more expensive than prototyping platforms.
Another class of acceleration platforms is simulation accelerators, or co-simulators. As the name suggests, co-simulators assist software simulators by running a portion of the design at a higher speed on a dedicated hardware platform. Typically, that part is synthesizable. The behavioral testbench is running on a host and communicates with the hardware platform using proprietary protocol over JTAG, Ethernet, PCI Express, or other high speed links. Xilinx ISIM simulator supports a co-simulation mode where part of the design runs on an FPGA.
Co-emulation is a more recent addition to the list of hardware acceleration tools. The primary distinction from a co-simulation is that the communications to the hardware platform is raised to the transaction level rather than being at the implementation level. In-circuit emulation(ICE) is not a platform, but instead is a method explaining how the hardware acceleration platform is used.
Architecture
Hardware acceleration platforms are designed using two main architectures based on FPGAs, or custom processors. FPGA-based platforms are usually cheaper, have faster emulation speed, and typically are used for ASIC prototyping. Emulation platforms are designed using hundreds, or even thousands of custom processors. They offer full design visibility, have higher capacity, and faster compile times.
Cost
Emulation platforms are usually more expensive than prototyping counterparts, and can easily reach several million dollars for the highest capacity configurations. Usually, the cost of a commercial hardware acceleration platform is proportional to its capacity.
Additional components that add to the cost of ownership include maintenance cost, the cost of verification libraries, transaction models, tool add-ons, and device emulators.
Typically, platform vendors provide a lease option. Because the emulation or prototyping platform is required only for a relatively short period of time, typically a few months till the design tape-out, it is more cost effective to lease it rather than buy.
Frequently used metrics to compare different platforms in terms of their cost are cost-per-gate, and cost-per-emulation-cycle.
Capacity
The capacity of an ASIC emulation or prototyping platform is typically measured in terms of equivalent 2-input ASIC gates. Using these metrics allows the comparison of the capacity of very different platform architectures. Capacity can range from several million ASIC gates to over a billion for high-end emulation platforms. Different approaches to perform ASIC design capacity estimate are discussed in Tip #38.
On-chip memory
Many ASIC designs require a significant amount of on-chip memory for embedded processors, system caches, FIFOs, packet buffering, and other applications. Emulation and prototyping platforms provide a wide range of memory capacities from Megabyte to a Terabyte.
Emulation Speed
Different approaches to perform emulation speed estimates are discussed in Tip #39.
Partition
A typical ASIC design is too large to fit into a single FPGA, and needs to be partitioned to run on a multi-FPGA platform. The partition process might be a complex optimization task that includes meeting platform’s cost, speed, and capacity goals, while ensuring proper connectivity between FPGAs, and reasonable complexity of the partition process. Different partitioning options are discussed in Tip
#48.
Software tools
Hardware acceleration platform vendors provide very different software tools, ranging from automated partitioning software, to IDE, optimized synthesis tool, and debugger. Good software tools are the key to improving verification productivity.
Custom platforms
Intel Atom prototyping platform
One of the designs prototyped on a custom Xilinx FPGA-based platform is the Intel Atom processor. The following picture shows the prototyping platform.
Figure 1: Intel Atom emulation platform (source: “Intel Atom processor core made FPGA-synthesizable”, Microarchitecture Research Lab, Intel corporation)
This platform is not available for general use, and is shown as an example of a custom platform.
Build vs. Buy
Modern high-end FPGAs certainly make the task of designing a custom hardware acceleration platform realistic. Several high-end FPGAs have enough capacity, user IOs, and embedded memory to emulate small to medium-size ASIC designs.
Building a custom FPGA-based hardware acceleration platform can offer a significantly higher emulation speed approaching the maximum speed that an FPGA supports. In some cases running the emulation at 200-300MHz is a realistic expectation.
A custom-built platform can have features or capabilities that commercial platforms don’t provide. For example, a custom-built platform can have a very high amount of external memory, a particular communication interface such as 10 Gigabit Ethernet, or a specific connectivity between FPGAs.
The main disadvantage of building a custom platform is significant design and bring-up time and effort. A hardware acceleration platform has a very short life cycle, from a few months to a year. By using an off-the-shelf platform, engineering teams can focus on ASIC design verification, rather than on building a short-lived platform.
Also, there is no definitive answer as to which approach is cheaper. There are several factors that affect the cost: the complexity of the custom-build platform, engineering effort, and the number of units to be manufactured.
Third party ASIC emulation and prototyping platforms
The following is a list of major ASIC emulation and prototyping platforms and tools.
Platform: Incisive Palladium Company: Cadence
http://www.cadence.com/products/sd/palladium_series/pages/default.aspx
Figure 2: Palladium systems (source: Cadence Palladium datasheet)
Cadence Incisive Palladium Enterprise Simulator is a high-performance emulation platform. It is based on multiple custom processor-based compute engines designed for running verification applications. Palladium provides easy-to-use compiler optimized for fast runtime, and a broad ecosystem of verification libraries, software tools, and hardware add-ons to support emulation and system level hardware/software co-verification. Key features of the platform are (source: Cadence Palladium datasheet):
Capacity: up to 2 Billion gates
Dedicated user memory: up to 1 Terabyte IO pins: up to 60 thousand
Emulation speed: up to 4 MHz
Compile time: 10-30MGate/hour on a single workstation Transaction and assertion-based accelerations
SpeedBridge adapters for connecting a wide range of peripheral devices using PCI Express, Ethernet, USB, AXI, and many other protocols.
Palladium is considered the market leader in providing hardware acceleration solutions for ASIC design verification.
Platform: Veloce
Company: Mentor Graphics
http://www.mentor.com/products/fv/emulation-systems/veloce
The Veloce product family is a high performance simulation acceleration and pre-silicon, emulation solution. It is based on multiple custom-designed processors. Veloce product line offers five scalable verification platforms with capacities from 8 million gates up to 512 million gates
Platform: ZeBu-Server Company: EvE
http://www.eve-team.com
ZeBu-Server is an FPGA-based system emulation platform with capacity of up to 1 Billion gates and emulation speed of up to 30MHz.
ZeBu-Server primarily aims at large-scale, multi-core chip and system emulation applications. ZeBu-Server is the highest performance emulator on the market. It uses Xilinx Virtex-5 LX330 FPGAs.
Products: RocketDrive, RocketVision Company: GateRocket
http://www.gaterocket.com
GateRocket offers RocketDrive, a small FPGA-based peripheral, which acts as accelerator for the HDL simulator, and RocketVision, a companion software debugging option.
Platform: HES Company: Aldec http://www.aldec.com
Aldec Hardware Emulation System (HES) allows using off-the-shelve prototyping FPGA boards for simulation acceleration and emulation. The strength of the tool is in automated design compilation, standard testing interface, and integration with leading hardware/software debugging tools such as Synopsys Certify.
Company: Dini Group
http://www.dinigroup.com/new/index.php
Dini Group offers high-capacity FPGA boards for ASIC prototyping and emulation systems. The following figure shows an FPGA-based prototyping platform from Dini Group using 16 Xilinx Virtex-5 FPGAs.
Figure 3: FPGA-based prototyping platform (courtesy of Dini Group)