”PUT” or writing tag SFB
6.4 Self-test Processing self-tests
The CPU executes the entire self--test program after POWER ON without backup voltage, for example, POWER ON after initial insertion of the CPU, or POWER ON without backup battery, and in TROUBLESHOOTING state. Theself-test takes approx.10 minutes.
When the CPU of a redundant system request a CPU memory reset and is then shut down with backup power, it performs a self--test irrespective of the backup function. The CPU requests a memory reset when you remove the Memory Card, for example.
The runtime operating system splits the self--test routine into several small program sections, namely the test slices,which are processed in multiple
successive cycles. The cyclic self--test is organized to perform a single, complete pass. The default time of 90 minutes can be modified in the configuration.
Reaction to errors during the self-test
If the self--test returns an error, the following happens:
Table 6-4 Reaction to errors during the self-test
Error class System reaction
Hardware error without
one--sided call of OB 121 The faulty CPU enters the DEFECTIVE state. Theredundant system changes over to stand--alone mode. The cause of the error will be written to the diagnostics buffer.
Hardware error with one-sided
call of OB121l The CPU with the one-sided OB121 enters theTROUBLESHOOTING state. The redundant system changes over to stand--alone mode (see below). RAM/PIQ comparison error The cause of the error will be written to the diagnostics
buffer.
The CPU enters the configured system or operating state (see below).
Checksum error The reaction depends on the error situation (see below).
Multiple--bit error The faulty CPU enters TROUBLESHOOTING state.
Hardware error with one-sided call of OB121l
If a hardware error occurs with a one-sided OB121 call for the first time since the previous unbuffered POWER ON, the faulty CPU enters the
TROUBLESHOOTING state. The redundant system changes over to stand--alone mode, and the cause of the error will be written to the diagnostics buffer.
RAM/PIO comparison error
If the self-test returns a RAM/PIQ comparison error, the redundant system quits redundant mode and the standby CPU partners the TROUBLESHOOTING state (default configuration). The cause of the error will be written to the diagnostics buffer.
The reaction to a recurring RAM/PIQ comparison error depends on whether the error occurs in the subsequent self-test cycle or not until later.
Table 6-5 Reaction to a recurring comparison error
Comparison error persists ... Reaction
in the first self-test cycle after
troubleshooting The standby CPU first enters theTROUBLESHOOTING state, and then goes into STOP.
The redundant system changes over to stand--alone mode.
after two or more self-test cycles after
troubleshooting Standby CPU enters theTROUBLESHOOTING state.
The redundant system changes over to stand--alone mode.
Checksum errors
The system reacts to initial checksum error detected after the last unbuffered POWER ON as follows:
Table 6-6 Reaction to checksum errors
Time of detection System reaction
During the POST The faulty CPU enters the DEFECTIVE state.
The redundant system changes over to stand--alone mode. In the cyclic self-test
(STOP or stand--alone mode)
The error will be rectified. The CPU remains in STOP or in stand--alone mode.
In the cyclic self-test
(redundant state) The error will be rectified. The faulty CPU entersTROUBLESHOOTING state.
The redundant system changes over to stand--alone mode. In TROUBLESHOOTING
state
The faulty CPU enters the DEFECTIVE state.
Single--bit errors The CPU calls OB84 after the detection and elimination of the error.
The cause of the error will be written to the diagnostics buffer.
In an F system, the F program is informed that the self-test has detected an error the first time a checksum error occurs in STOP or stand--alone mode. The reaction of the F program to this is described in the S7-400F and S7-400FH Programmable Controllers manual.
Hardware error with one--sided call of OB121, checksum error, second occurrence
The 41x-4H CPU reacts to a second occurrence of a hardware error with
one--sided call of OB121 and of a checksum error as described in the table below, based on the various operating modes of the 41x-4H CPU.
Table 6-7 Hardware error with one--sided call of OB121, checksum error, second occurrence
Error CPU in stand--alone
mode CPU in stand--alonemode CPU in redundant mode
Hardware error with one-sided call of OB121
OB121 is being executed OB121 is being executed The faulty CPU enters TROUBLESHOOTING state. The redundant system changes over to stand--alone mode, Checksum
error The CPU enters theDEFECTIVE status if two errors occur within two successive test cycles. (Configure the length of the test cycle in HW Config)
The CPU enters the DEFECTIVE status if two errors occur within two successive test cycles. (Configure the length of the test cycle in HW Config)
The CPU enters the DEFECTIVE status if a second error occurs within the troubleshooting state which was triggered by the first error event.
The CPU when operating on stand--alone or stand--alone mode reacts to a second checksum error as it did on the first occurrence of the error, after twice the test cycle time has expired. A CPU operating in redundant mode reacts to a second error (hardware error with one--sided call of OB121, checksum error) as it did on the first occurrence of the error and when troubleshooting is concluded.
Multiple--bit errors
The CPU enters the TROUBLESHOOTING state when a multiple--bit error is detected while the redundant system is operating in redundant mode. When troubleshooting is concluded, the CPU can automatically couple and update itself in order to resume redundant operation. At the transition to troubleshooting mode, the address of the triggering error is reported in the diagnostics buffer.
Single--bit errors
Controlling the cyclic self--test
SFC90 H_CTRL allows you to control the scope and execution of the cyclic self-test. For example, you can remove various test components from this scope, or and include these again. In addition, you may explicitly call specific test components, and then initiate processing of these.
For detailed information on SFC90 H_CTRL, refer to the System Software for S7-300/400, System and Standard Functions manual.
Notice
In a fail-safe system, you may not disable and then re--enable the cyclic self-tests. For more details, refer to the S7-400F and S7-400FH Programmable Controllers manual.