SEPARATE-CAMS SCHEME FOR RUNTIME POWER REDUCTION

As highlighted in chapter 1, if we do not employ SRDF test algorithms we need to store in the CAM during diagnosis all faulty memory words, in order to determine those comprising more than one faulty cell. On the other hand, for repair purposes we need to store in the CAM only the words comprising more than one faulty cell. Thus, to reduce runtime power we use a large CAM for diagnosis purposes (diagnosis- CAM). Then, at the end of the test and diagnosis phase we transfer the memory words comprising multiple faulty cells in a separate small CAM (runtime-CAM). At runtime, only this CAM is used and powered. As it is drastically smaller than the diagnosis-CAM (which has the same size as the CAM used in conventional repair), it consumes drastically lower power than conventional repair. Note also that, though the diagnosis-

CAM of this scheme has the same size as the CAM used in conventional repair, it may also allow significant area reduction with respect to conventional self-repair. Indeed, after fabrication, the diagnosis information has to be stored in non-volatile embedded memory, to guarantee that faulty memory locations detected and diagnosed by thorough fabrication tests are permanently stored in the chip after power shutdown. Conventional self-repair will save in non-volatile memory all faulty memory words, while, in ECC-based repair, only words comprising multiple faulty cells will be stored in non-volatile memory. Thus, drastically smaller non-volatile memory is required.

Let us now describe the operation of the separate-CAMs scheme.

Each location of the diagnosis-CAM and the runtime-CAM is composed of a tag field in which we store the addresses of faulty words of the memory under repair, and a data field in which we store the positions of the faulty cells of these words. Each CAM location also possesses a flag cell (flag1) used to indicate bad CAM locations. In both, the diagnosis-CAM and the runtime-CAM the flag1 cells are initialized to 0, and during the test sessions of these CAMs, flag1 is set to 1 in each bad CAM location (i.e. a CAM location that cannot be used for repair because it contains faults in the tag field or in the flag cells, or more than one faulty data cells). If a flag1 cell is faulty, it may indicate as good for performing repair a bad CAM word. To avoid this problem, a second flag cell (flag1’) can be added in each CAM location [19]. Another flag cell (flag2) is used to indicate that the CAM location is not free (i.e. it is occupied by information concerning a faulty memory word).

Let us now discuss the operation of the diagnosis-CAM during the test and diagnosis of the memory under repair. When the current read operation of the test algorithm detects a faulty memory word, the contents of the diagnosis-CAM have to be updated. Thus, the address of the faulty memory word is compared with all the tag fields of this CAM. This comparison is performed by a comparator integrated in each tag field. The tag field also includes circuitry that deactivates the match signal if flag1 = 1 or flag2 = 1. Thus, a hit occurs only if: the tag comparison matches (meaning that the faulty address is already stored in the tag field of a CAM location); flag1 = 0 (meaning that the CAM location is good); and flag2 = 0 (meaning that the CAM location is occupied by diagnosis information of a faulty memory word). Then, two CAM-updating mechanisms are used (Hit-updating and Miss-updating).

- Hit-updating: In case of hit, the activated match line selects the data field of the hit CAM location, in which we update the positions of the faulty cells of the memory word. This update is done by: reading the content of the selected data field; bit-wise ORing it with a vector containing the faulty- cell positions of the faulty memory word; and writing the result back to the selected data field. Note that the vector containing the faulty-cell positions of the faulty memory word is obtained from the current outputs of the XOR gates of the BIST comparator.

- Miss-updating. In case of miss, a free CAM location has to be selected for storing the faulty address and the positions of the faulty cells. This selection mechanism uses a counter (to be referred as FLC – free-locations counter), whose content identify a free CAM location. The content of FLC is decoded to activate the word-line selecting the tag field and the data field of this location6. Then, the address of the faulty word is written in the selected tag field, the vector containing the faulty-cell positions is written in the data field, and the value 0 is written in the flag2 cell to indicate that the CAM location is occupied (it contains diagnosis information of a faulty memory word).

Before starting the test and diagnosis phase of the memory under repair, the tag fields and the data fields of the diagnosis CAM are set to 0, and the flag2 cells are set to 1. The FLC counter is also reset. If the first CAM location selected by FLC has flag1 = 1 FLC increments, and this is repeated each time the next location has flag = 1.

6 _{Alternatively a shift-register containing 1 in one position and 0 in all other positions can be used instead of the counter FLC}

Test and diagnosis process:

During the test and diagnosis phase of the memory under repair, each time a fault is detected in this memory, the diagnosis-CAM is updated by means of the Hit-updating or the Miss-updating mechanism as described above. In addition, when Miss-updating is activated, FLC is incremented. If the new location pointed by FLC has flag1 = 1, then FLC increments again. Thus, FLC always points a good CAM location (which is also unoccupied because diagnosis information is stored only in locations already visited by FLC).

At the end of the test and diagnosis phase, FLC is used to visit and read each location of the diagnosis- CAM. For each diagnosis-CAM location having flag1= 0, flag2 = 0, and containing multiple 1’s in the data field, the tag field is transferred to a good location of the runtime-CAM7 (and to the non-volatile memory if any), and the flag2 cell of this location of the runtime CAM is set to 1. To select sequentially the locations of the runtime-CAM during this transfer, we employ a mechanism using a counter similar to FLC.

Runtime operation:

Similarly to the diagnosis-CAM, each location of the runtime-CAM includes a comparator and extra circuitry that deactivates the match signal if flag1 = 1 or flag2 = 1. Thus, a hit occurs in the runtime-CAM only if the tag comparison matches, flag1 = 0 (meaning that the CAM location is good), and flag2 = 0 (meaning that the CAM location is occupied by a faulty memory word). At runtime, reads and writes are performed over the memory, but, at the same time the runtime-CAM compares in parallel the address of the current memory operation with its tag fields. In case of hit: if the memory operation is a write, the data are also written in the data field of the hit CAM location; if the memory operation is a read, the data field of the hit CAM location is read and the read data are supplied to the data bus of the system. To do this, the hit signal controls a multiplexer. Then, each time this signal is active it disconnects the memory from the data bus and connects instead the runtime-CAM. As the runtime-CAM is small even for high defect densities, and it is accessed in parallel with the memory, it will not induce performance penalty. Thus, the only performance penalty is due to the MUX added in the data bus. On the contrary, conventional repair in high defect densities will require very large CAM, which will induce non-negligible performance penalty.