Serial Lite III Streaming Source Core

The source core consists of four major functional blocks (the implementation varies depending on the clocking mode):

• Source application module

• Source adaptation module

• L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP and Transceiver Native PHY IP TX core for Intel Arria 10 - Interlaken mode

• Interlaken PHY v18.1 IP TX core (Stratix V and Arria V GZ devices)

• Clock generator (in the standard clocking mode for Intel Arria 10, Stratix V, and Arria V GZ devices)

Related Information

• Standard Clocking Mode in Serial Lite III Streaming Intel FPGA IP Core (Intel Stratix 10 Devices) on page 75

5. Serial Lite III Streaming IP Core Functional Description UG-01126 | 2019.01.17

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• Standard Clocking Mode in Intel Arria 10, Stratix V, and Arria V Devices on page 79

• Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core (Intel Stratix 10 Devices) on page 82

• Advanced Clocking Mode Structure For Intel Arria 10, Stratix V, and Arria V Devices on page 85

5.1.1.1. Source Application Module

The application module performs the following functions:

• Burst encapsulation—inserts burst control words into the data stream to define the beginning and the end of streaming data bursts.

• Idle insertion—inserts idle control words into all lanes of the data stream interface.

5.1.1.2. Source Adaptation Module

This module provides adaptation logic between the application module and the L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP core or Transceiver Native PHY in Intel Arria 10 devices or Interlaken PHY v18.1 IP (Stratix V and Arria V GZ devices) core. The adaptation module performs the following functions:

• Rate adaptation—includes a dual-clock FIFO buffer to cushion the Interlaken PHY v18.1 IP core's burst read requests and to provide a streaming user write interface. The FIFO also transfers streaming data between the user_clock and tx_coreclkin clock domains.

• Control signal translation—include state machines that map the control signal semantics on the framing interface

⁽⁴⁾

to the semantics of the Transceiver Native PHY or Interlaken PHY v18.1 IP core TX interface.

• Non-user idle insertion—inserts non-user idle control words in the absence of user data to manage the minimum data rate requirements of the Interlaken protocol.

The control words are removed by the sink adaptation module in the Serial Lite III Streaming IP core link partner.

• ECC correction and ECC fatal error detection

5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode For Intel Arria 10 and Intel Stratix 10 with L-tile and H-tile devices, this block is an instance of the Native PHY IP core configured for Interlaken - TX only operation. The PMA width for Interlaken mode is 64 bits.

For Stratix V and Arria V GZ devices, the Interlaken PHY IP TX core is an instance of the Interlaken PHY IP core configured for TX only operation. The PMA width for Interlaken mode is 40 bits. The core requires a Transceiver Reconfiguration Controller for transceiver calibration. The number of channels programmed for configuration in the Transceiver Reconfiguration Controller depends on the IP core's operation mode.

For example, if the design is a source core only design or a duplex core design, the reconfiguration interfaces is equal to the number of lanes x 2.

(4)

The framing interface is to frame every data burst with the Start of Burst, Sync, and End of Burst, and sequence them to the PHY interface.

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Related Information

• Intel Arria 10 Transceiver PHY User Guide

For more information about the Intel Arria 10 Native PHY IP core.

• Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

For more information about the Stratix 10 L- and H-Tile Native PHY IP core.

• Intel Stratix 10 E-Tile Transceiver PHY User Guide

For more information about the Intel Stratix 10 E-Tile Native PHY IP core.

• V-Series Transceiver PHY IP Core User Guide

For more information about the Interlaken PHY IP core and reconfiguration controller.

5.1.1.4. Source Clock Generator

When you use standard clocking mode for the user interface, the IP core provides a clock generator to generate the user clock ( user_clock ) and the Intel Arria 10 Transceiver Native PHY ( tx_coreclockin ) or Interlaken PHY v18.1 IP ( tx_clkout ) core clock signals. This clock generator consists of a fPLL (Stratix V and Arria V GZ) or I/O PLL (Intel Arria 10) and a state machine responsible for clocks generation and reset sequencing. The user_clock_reset is not released until the fPLL or I/O PLL is locked. The module is used in the standard clocking mode only.

Note: For Intel Stratix 10 devices, the tx_clkout signal provides the clock for L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 IP core clock signal (tx_coreclockin) because there is no clock generator module in the Serial Lite III Streaming IP core.

Figure 9. Clock Generator Block Diagram

Reset State Machine fPLL/IO PLL

phy_mgmt_clk_reset tx_coreclkin user_clock

lock

user_clock_reset tx_clkout

• For all Stratix V and Arria V GZ devices, the fPLL generates the user_clock/

user_clock_tx and tx_coreclkin based on fixed ratios determined by the Serial Lite III Streaming parameter editor.

• For Intel Arria 10 devices, the I/O PLL generates the user_clock/

user_clock_tx based on a fixed ratio, however, the tx_coreclkin operates at the same frequency as tx_clkout .

Related Information

• Standard Clocking Mode in Serial Lite III Streaming Intel FPGA IP Core (Intel Stratix 10 Devices) on page 75

5. Serial Lite III Streaming IP Core Functional Description UG-01126 | 2019.01.17

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• Standard Clocking Mode in Intel Arria 10, Stratix V, and Arria V Devices on page 79

• Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core (Intel Stratix 10 Devices) on page 82

• Advanced Clocking Mode Structure For Intel Arria 10, Stratix V, and Arria V Devices on page 85

• Sink Clock Generator on page 36

In document Serial Lite III Streaming Intel FPGA IP Core User Guide (Page 32-35)