Completion of an integrated system design is the final step in the design and implementation of the VHDL and FPGA Offset PPM coding system. However, such compromises need not be required, given the processing power of modern FPGA and the high design capability of VHDL, if sufficient programming and design expertise be used in the design and coding, however complex the system. The Altera Quartus II software package was used for the first implementation of the Offset PPM system. A RESET signal was provided by one of the eight IP switched and the input clock was provided by a 50 MHz oscillator. Five stages constituted the transmitter side:
• PLL for the 1 MHz clock. • PRBS generator.
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• PISO for parallel PRBS output to serial conversion. • Offset PPM encode.
The transmitter output is sent through a modelled channel.
At the receiver end, the data is processed in four steps. These included the Offset PPM decoder and the SIPO.
The following figure (6.21) shows a framework of Offset PPM layout. Figure (6.22) illustrates Offset PPM system.
Figure 6-21 Serial Offset PPM system layout
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The final stage of the design and implement of the Offset PPM coding system using VHSIC hardware description language (VHDL) and field programmable gate array (FPGA) required complete an integrated system design. Figure (6.23) shows the VHDL implementation of the full serial Offset PPM system. The first serial Offset PPM was implemented using the components that are described in the previous sections. Figure (6.24) illustrates the modification of serial Offset PPM system, this figure shows that serial Offset PPM encoder and decoder in one block. These serial encoder and decoder are consisting of SIPO and PISO together with the parallel Offset PPM encoder and decoder.
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The simulation report was generated based on the same waveform file after the compilation of the modified circuit was completed. The simulation waveform of the Offset PPM system is given in figure (6.25). The waveform is annotated and it is clearly noticeable that the Offset PPM data has been successfully decoded into the original PCM data according to the theoretical table given in chapter 4 (Table 4.1). There is a delay between the input PCM and the output PCM as shown by the in the figure (6.25). The PCM input data is named (prbs), while the PCM output data named (decoder_op). The red arrow on the figure indicates a reference points on the two signals to show the similarity between them, and the delay which occurs.
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Quartus® II software includes a system level debugging tool called Signal Tap Analyser (STA) that can be used to capture and display signals in real time in any FPGA design. STA Logic Analyser is scalable, easy to use, and is available as a stand-alone package or included with the Quartus® II software subscription. This logic analyser helps debug an FPGA design by probing the state of the internal signals in the design without the use of external equipment. After the program was successfully downloaded to the FPGA board through the programmer, the result of analysis to evaluate the practical performance was obtained once the analysis process was completed. There is a delay between the input PCM and the output PCM as shown by the in the figure (6.26).
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Experimental verification results of the Offset PPM decoder are given in figure (6.27). There is a delay between the PCM output and decoded PCM similar to figure (6-26) in the previous page, the red boxes indicate reference points in the two signals to show waveforms clearly in the same screenshot.
Figure 6-27 PRBS output (top trace), Offset PPM decoder (bottom trace)
6.8 Summary
• In this chapter, the Cyclone III development board and SMA Breakout Cable were described with the lists of features of the board and specific information.
• The Offset PPM system has been discussed and implemented using VHDL with fully successfully testing results in this chapter.
• This work was executed using VHDL on an FPGA. The encoder and decoder design and development have been described and the simulation waveforms and practical results of the implementation have all been presented in this chapter.
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7 Optical Offset PPM Communication System
7.1 Introduction
Chapter 6 presented and discussed the design of the Offset PPM system’s VHDL source code and the implementation of the system. In order to implement the full optical communication designed system, Altera Quartus II was used in conjunction with a Cyclone III Field Programmable Gate Array (PFGA) based DSP development board (Altera, 2015). The design stage for the voltage comparator, optical receiver and optical transmitter was completed and these entities were then created. In order to obtain the digital input signals and output signals from the FPGA, the author adopted the SMA breakout cable interface. Figure (7.1) illustrates the framework of the full Offset PPM communication system with optical communication set as a first test, while, figure (7.2) shows the second test for this communication system using an external PRBS generator. The test bench equipment is demonstrated in figure (7.3).
Figure 7-1 Frame work of the full Offset communication system
Offset PPM encoder Offset PPM decoder PRBS PC
FPGA SMA Cable Oscilloscope
Optical Receiver
Optical
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Figure 7-2 Frame work of the full Offset communication system with external PRBS
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