Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-put). See Figure 19-1 below.
Figure 19-1. Serial Programming and Verify
Note: If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
Note: In Table 19-10 above, the pin mapping for SPI programming is listed. Not all devices use the SPI pins dedicated for the internal SPI interface.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Table 19-10. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PA6 I Serial Data in
MISO PA5 O Serial Data out
SCK PA4 I Serial Clock
VCC
GND SCK
MISO MOSI
RESET
+1.8 - 5.5V
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:
• Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
• High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
19.5.1 Serial Programming Algorithm
When writing serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of SCK.
When reading, data is clocked on the falling edge of SCK. See Figure 20-3 and Figure 20-4 for timing details.
To program and verify the ATtiny24A/44A/84A in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 19-12):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at least tRST (the minimum pulse width on RESET pin, see Table 20-4 on page 182) plus two CPU clock cycles.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-chronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 3 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 19-11 on page 170.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 19-11 on page 170.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If poll-ing (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 19-11 on page 170). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
19.5.2 Serial Programming Instruction set
The instruction set is described in Table 19-12 and Figure 19-2 on page 171.
Table 19-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 4.0 ms
tWD_ERASE 9.0 ms
tWD_FUSE 4.5 ms
Table 19-12. Serial Programming Instruction Set
Instruction/Operation(1)
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Programming Enable $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte $4D $00 Extended adr $00
Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in
Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 adr LSB data byte in
Read Instructions
Read Program Memory, High byte $28 adr MSB adr LSB high data byte out
Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 $00 adr LSB data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 adr LSB data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Extended Fuse Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out
Write Instructions(6)
Write Program Memory Page $4C adr MSB adr LSB $00
Write EEPROM Memory $C0 $00 adr LSB data byte in
Write EEPROM Memory Page (page access) $C2 $00 adr LSB $00
Notes: 1. Not all instructions are applicable for all parts.
2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See http://www.microchip.com for Application Notes regarding programming and programmers.
Figure 19-2. Serial Programming Instruction example
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
Write Lock bits $AC $E0 $00 data byte in
Write Fuse bits $AC $A0 $00 data byte in
Write Fuse High bits $AC $A8 $00 data byte in
Write Extended Fuse Bits $AC $A4 $00 data byte in
Table 19-12. Serial Programming Instruction Set (Continued)
Instruction/Operation(1)
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Byte 1 Byte 2 Byte 3 Byte 4
Adr LSB
Bit 15 B 0
Serial Programming Instruction
Program Memory/
EEPROM Memory
Page 0
Page 1
Page 2
Page N-1 Page Buffer
Write Program Memory Page/
Write EEPROM Memory Page Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1 Byte 2 Byte 3 Byte 4
Bit 15 B 0
Adr MSB
Page Offset
Page Number Adr MMSSB
A AAdrr LLSBB
After data is loaded to the page buffer, program the EEPROM page, see Figure 19-2 on page 171.