SETB 2BH Discussion

Byte address 25H is within the bit-addressable area of internal memory (see Figure 2-7).

The bit addresses within this byte, starting at bit 0, are 28H, 29H, etc. Bit 3 within byte ad-dress 25H is at bit adad-dress 2BH.

2.5.3 Register Banks

The bottom 32 locations of internal memory contain the register banks. The 8051 instruc-tion set supports eight registers, R0 through R7, and by default (after a system reset) these registers are at addresses 00H-07H. The following instruction, then, reads the contents of address 05H into the accumulator:

MOV A,R5

This instruction is a 1-byte instruction using register addressing. Of course, the same oper-ation could be performed in a 2-byte instruction, using the direct address as byte 2:

MOV A,05H

Instructions using registers R0 to R7 are shorter than the equivalent instructions using direct addressing. Data values used frequently should use one of these registers.

The active register bank may be altered by changing the register bank select bits in the program status word (discussed below). Assuming, then, that register bank 3 is active, the following instruction writes the contents of the accumulator into location 18H:

MOV R0,A

The idea of "register banks" permits fast and effective "context switching," whereby separate sections of software use a private set of registers independent of other sections of software.

EXAMPLE What is the address of register 5 in register bank 3?

2.2 Solution

1 D H Discussion

Register bank 3 occupies internal memory locations 18H to 1FH (see Figure 2-7), with R0 at address 18H, R1 at address 19H, etc. Register 5 (R5) is at address 1DH.

2.6 SPECIAL FUNCTION REGISTERS

Internal registers on most microprocessors are accessed implicitly by the instruction set.

For example, "INCA" on the 6809 microprocessor increments the contents of the A accu-mulator. The operation is specified implicitly within the instruction opcode. Similar access to registers is also used on the 8051 microcontroller. In fact, the 8051 instruction "INC A"

performs the same operation.

The 8051 internal registers are configured as part of the on-chip RAM: therefore, each register also has an address.¹This is reasonable for the 8051, since it has so many reg-isters. As well as R0 to R7, there are 21 special function registers (SFRs) at the top of internal RAM, from addresses 80H to 0FFH. (See Figure 2-7 and Appendix D.) Note that most of the 128 addresses from 80H to 0FFH are not defined. Only 21 SFR addresses are defined (26 on the 8032/8052).

Although the accumulator (A or ACC) may be accessed implicitly as shown previ-ously, most SFRs are accessed using direct addressing. Note in Figure 2-7 that some SFRs are both bit-addressable and byte-addressable. Programmers should be careful when ac-cessing bits versus bytes. For example, the instruction

S E T B 0 E 0 H

sets bit 0 in the accumulator, leaving the other bits unchanged. The trick is to recognize that 0E0H is both the byte address of the entire accumulator and the bit address of the least-significant bit in the accumulator. Since the SETB instruction operates on bits (not bytes), only the addressed bit is affected. Notice that the addressable bits within the SFRs have the five high-order address bits matching those of the SFR. For example, Port 1 is at byte address 90H or 10010000B. The bits within Port 1 have addresses 90H to 97H, or 10010xxxB.

1The program counter and the instruction register are exceptions. Since these registers are rarely manipulated directly, nothing is gained by placing them in the on-chip RAM.

EXAMPLE What instruction could be used to set the most-significant bit in the B accumulator while 2.3 leaving the other bits intact?

Solution

S E T B 0 F 7 H Discussion

The B accumulator is at byte address 0F0H in the special function register space of internal memory (see Figure 2-7). Individual bits are accessible, with bit 0 at address 0F0H, bit 1 at address 0F1H, etc. Bit 7 of the B accumulator is at bit address 0F7H.

The PSW is discussed in detail in the following section. The other SFRs are briefly introduced following the PSW, with detailed discussions deferred to later chapters.

2.6.1 Program Status Word

The program status word (PSW) at address 0D0H contains status bits as summarized in Table 2-3. Each of the PSW bits is examined below.

2.6.1.1 Carry Flag The carry flag (C or CY) is dual-purpose. It is used in the traditional way for arithmetic operations: set if there is a carry out of bit 7 during an add, or set if there is a borrow into bit 7 during a subtract. For example, if the accumulator contains 0FFH, then the instruction

A D D A , # 1

leaves the accumulator equal to 00H and sets the carry flag in the PSW.

EXAMPLE What is the state of the carry flag and the content of the accumulator after execution of the

The binary addition that occurs in the third instruction is illustrated below.

01010101 (R5 = 55H) +10101010 (ACC = 0AAH)

11111111 (Result in ACC = 0FFH)

The addition does not generate a carry of the most-significant bit (bit 7); therefore, the carry bit is cleared. The final result in the accumulator is 0FFH = 255₁₀.

The carry flag is also the "Boolean accumulator," serving as a 1-bit register for Boolean instructions operating on bits. For example, the following instruction ANDs bit 25H with the carry flag and places the result back in the carry flag:

ANL C,25H

2.6.1.2 Auxiliary Carry Flag When adding binary-coded-decimal (BCD) values, the auxiliary carry flag (AC) is set if a carry was generated out of bit 3 into bit 4 or if the result in the lower nibble is in the range 0AH-0FH. If the values added are BCD, then the add instruction must be followed by DA A (decimal adjust accumulator) to bring results greater than 9 back into range.

EXAMPLE What is the state of the auxiliary carry flag and the content of the accumulator after 2.5 execution of the instruction sequence below?

MOV R5,#1

The binary addition that takes place in the third instruction is illustrated below.

1

00000001 (R5 = 01H) +00001001 (ACC = 09H)

00001010 (Result in ACC = 0AH)