c-Si bulk optimization for PERT

The architecture of the bottom silicon cell must be reconsidered with these new design requirements. Concerning the silicon bulk properties, the bulk resistivity and background doping type will have an impact on the minority carrier collection and therefore cell performance. Here we firstly simulate the PERT structure we used in our previous work to better understand the impact of these parameters on the performance of the tandem

structure. We set the wafer to be 280 μm thick, which gives reasonably low optical losses

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the complete perovskite/c-Si monolithic device is done by SunSolve202

using the structure given in Figure6.2.2, which applies conventional ray tracing and accounts for thin-film optics by the transfer matrix method. For easy comparison, all the c-Si cell structures investigated in the remainder of this work are simulated with the same generation profile. The generation profile of the c-Si bulk results in a photogenerated current Jsc of 19.98

mA/cm2

. Shading was included to account for the front metal dots in the structure. (For later structures without such metal vias, the shading fraction is set to zero, resulting in slightly higher Jsc). Here we sweep four different structures by considering the possible

combinations of front/rear junction and n/p-type bulk doping. The parameters used in the simulation are obtained from our previous work51

and the literature157,205,206

as illustrated in Table 6.3, the rear side is 1.6× the front value for J0-diffused due to larger textured surface area.207

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Figure 6.3.1. Simplified device structure diagram for the perovskite/c-Si monolithic tandem device using PERT structure bottom c-Si cell with (a) n-type front junction, (b) n-type rear junction, (c) p-type front junction, and (d) p-type rear junction.

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Figure 6.3.2. The simulated efficiency of the PERT c-Si bottom cell in relation to the bulk resistivity and lifetime with (a) n-type wafer with front junction structure, (b) n-type wafer with rear junction structure, (c) p-type wafer with front junction structure, and (d) p-type wafer with rear junction structure.

Figure 6.3.3. The simulated Voc of the PERT c-Si bottom cell in relation to the bulk resistivity and lifetime with

(a) n-type wafer with front junction structure, (b) n-type wafer with rear junction structure, (c) p-type wafer with front junction structure, and (d) p-type wafer with rear junction structure.

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Figure 6.3.4. The simulated Jsc of the PERT c-Si bottom cell in relation to the bulk resistivity and lifetime with (a)

n-type wafer with front junction structure, (b) n-type wafer with rear junction structure, (c) p-type wafer with front junction structure, and (d) p-type wafer with rear junction structure.

Figure 6.3.5. The simulated Voc of the HJT c-Si bottom cell in relation to the bulk resistivity and lifetime with (a)

n-type wafer with front junction structure, (b) n-type wafer with rear junction structure, (c) p-type wafer with front junction structure, and (d) p-type wafer with rear junction structure.

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Figure 6.3.6. (a) IV simulation result of the bottom PERT c-Si cell in a monolithic tandem before and after the bulk resistivity and doping optimization. (b) Power losses using a free energy loss analysis (FELA) for different

bulk configurations at the maximum power point with optimized resistivity (1 Ω·cm) and 1800 µs for the bulk

lifetime. For ease of reading, optical and generation losses are not presented.

Since the wafer is significantly thicker, a high bulk lifetime is more important in a tandem configuration to ensure a sufficiently high diffusion length. The FF and short circuit current density become two competing parameters for the cell performance with the change of bulk resistivity. From the simulation results, as shown in Figure6.3.2, a wafer resistivity of ~1 Ω·cm is found to be ideal for fabricating high-performance devices with the PERT structure simulated. Among the four different scenarios, cells with p-type wafers show improved cell performance for the same bulk lifetime, mainly attributed to an increased fill factor. The higher mobility of minority carriers in p-type wafer provides a longer diffusion length when they travel through the bulk at the maximum power point. Series resistance exists in c-Si bulk along the carrier collection path. Since the wafer thickness is increased, the resistivity of the wafer needs to be low to have low majority carrier transport loss, but it will compete with the mobility of the minority carriers. A low resistivity wafer means higher doping concentration, which effectively enhances the chance of minority carrier scattering and hence brings down minority carrier mobility.208 _{A higher resistive loss will decrease the}

FF209

and the reduced mobility of the minority carriers has a negative impact on Jsc and Voc.

Therefore, we have competing requirements for optimising Jsc, Voc and FF in Figure6.3.3-

6.3.5 when varying the bulk resistivity. From Figure6.3.6(b) it can be seen that, by switching the wafer background doping from n-type to p-type, bulk recombination is suppressed

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because electrons have higher mobility than holes as minority carriers and result in a higher effective diffusion length for minority carriers in the p-type wafer.

Comparing the front and rear junction designs, we find that the rear junction has a slight advantage over the front junction. Minority carriers must diffuse to the junction, which requires a concentration (since Jp,diff = qDp·dp(x)/dx where Dp is the diffusivity of holes and p(x) is the

concentration). This means that their concentration will be higher at the interface opposite the junction, particularly for the case of the relatively flat generation profile in the c-Si cell in tandem configuration. Since the recombination rate at either surface is given by the product of the surface recombination parameter (J0) and the carrier concentration at that surface, total surface

recombination is minimised if the surface with the higher carrier concentration coincides with the region with the lower J0, which therefore favours a rear junction cell design. As shown in

Figure 6.3.6, the recombination loss at the front surface is significantly increased but it decreases at the rear surface when switching from the front junction to rear junction, due to the reason given above.

The loss analysis also shows that the efficiency loss is dominated by surface recombination and contact resistive losses. Hence, the bulk optimisation resulted in only modest improvements in the device performance. Without changing the processing conditions of the monolithic tandem device, by bulk optimisation, a 0.35% absolute efficiency increase from the bottom c-Si cell can be achieved compared with 5 Ω·cm n-type wafers we used in our previous work if a similar bulk lifetime can be maintained.