A single receiver component such as the MIMO demapper cannot be designed with- out considering the effects of the other components and their settings. This is a result of mutual dependencies. On the one hand, the demapper component is influenced by the other components, for instance by the channel model and the transmitter setup. On the other hand, the demapper influences other components such as the channel decoder. Therefore, for both the architecture design and the algorithm development, a simulator modeling the essential effects of a MIMO transmission is essential. Fig- ure 4.2 visualizes an exemplary setup of transmitter, channel and receiver components required for a realistic simulation of a MIMO transmission according to the baseband model discussed in Chapter 3.
4.2.1
Simulation Design and Setup
Depending on whether a simulator should comply with a single standard or enable a more general investigation of transceiver algorithms and architectures, the required amount of configurability and the resulting degrees of freedom change significantly. Particularly in the latter case, which is the relevant one for this work, a high degree of configurability is required. The simulated scenario is determined by various setup options for the transmitter, the channel and the receiver and its components. Very common options are parameters and algorithm selections for channel encoders as well as decoders, different modulation schemes and antenna setups, various channel mod- els, etc. Thus, fixed settings on the transmitter side and the receiver side need to be matched in such a physical-layer simulator unless higher protocol layers are included in the simulation in order to use in-band control channels for the synchronization of the transmission settings. These scenario settings cause tight dependencies between transmitter and receiver components in a pure physical-layer simulator. This focus on the pure physical layer requires a system-wide handling of configuration options but removes the necessity for the handling and scheduling of configuration transitions in- side receiver blocks. Simulating different scenarios (e.g. SNRs, channel models, etc.)
4.2. Simulation and Verification Considerations 75 encoder encoder encoder source Π mapper channel model channel model channel model demapper ... Π−1 decoder decoder decoder Π
transmitter setup channel setup receiver setup
analysis FER, ...
architecture development
LISA processors RTL, gate level FPGA
verification p ro b es co -s im u la ti o n
Figure 4.2: Simulation and verification for a demapper for the MIMO physical layer.
and setups (channel codes, modulation, etc.) then requires several simulation runs and a data aggregation step for the analysis.
Functional blocks like the channel estimation, the channel model and the data source may require internal states in order to track for instance random generator states or the channel state. Therefore, a pure functional implementation is not rea- sonable for most of the blocks. Data-driven approaches such as followed by Synopsys System Studio and Synopsys SPW [176] or Simulink [182] are better suited. These approaches support a separation of the data processing inside the functional blocks and the scheduling required for serving these blocks with data, typically aggregated to chunks of a size preferred by a block. This concept implies that transmitter and re- ceiver blocks are simulated quasi concurrently, i.e. several data chunks are processed in a pipeline-like manner in the various blocks of the transmitter, channel or receiver. Although a data-driven approach already links to the data processing of a transceiver architecture, this approach typically results in an untimed pure functional algorithmic simulation. For a more hardware-centric approach, system-simulation concepts as re- alized e.g. by SystemC [135] can provide various abstraction levels between functional simulation with timing estimations down to cycle-accurate system simulation.
76 Chapter 4. From Algorithm to Architecture: An Integrative MIMO Simulation Testbed
4.2.2
Simulation Analysis
In a simulator for wireless communications, the simulation result of a single setup/ scenario is usually characterized by error rates (e.g. FER, BER, etc.). Determining these error rates requires a special data handling in a pipelined data-driven simulation. Therefore, the analysis unit needs to buffer the input data and synchronize it with the received bit or symbol stream. When iterations between the demapper and the decoder are included in the receiver, it can be beneficial to calculate error rates also for intermediate iterations. Hereby, error-rate information can be obtained for all iteration settings I′ ∈ {1, ..., I} in a single simulation with I iterations.
Aside from error-rate information, further statistical information can be relevant for the analysis of a single set of parameters. Particularly in the case of MIMO demap- ping with sphere decoders, their variable runtime depends significantly on the sce- nario, the transmission parameters and the receiver setup. Therefore, it is essential to include an analysis facility for tracking statistics such as the number of examined nodes Ne during a simulation and also separately per iteration I′.
4.2.3
Architecture Development and Verification
Figure 4.2 shows two different intents of an architecture development and verification process which is tightly integrated in to the simulation of a wireless transmission. One aspect is verification by using a bit-true functional simulation as a reference to verify an architecture by its input/output behavior in a black-box test or by a white-box test including internal intermediate values and states. The other aspect is co-simu- lation which feeds back the results from the architectural simulation back into the algorithmic simulator. The latter approach can be used beneficially to conveniently characterize an architecture for a certain scenario or setup. Particularly when used with FPGA prototypes, this approach can speed up the characterization and verifica- tion significantly.
The integration of verification and co-simulation features into a simulator requires the integration of probes in the simulator design. These probes need to redirect data and control information to either dump files in the case of loosely coupled hard- ware verification or to inter-process communication (IPC) facilities provided by the simulator host operating system. Hardware simulators or accelerators that are only available at remote machines can be accessed via network communication. For such IPC or network links, particularly for FPGA accelerators, communication latencies can become the dominating factor for simulation speeds. Typical counter-measures include the aggregation and transfer of larger data chunks at once, for instance whole code words instead of single symbol vectors in the case of a demapper.