Multi-processor simulation
5.4 Simulation results
5.4.1 Initialization
There are two processors (the same number of processors as in the SpiNNaker test chip), a Fascicle and a Monitor Processor, in each chip of the four-chip model. The Fascicle and the Monitor Processor load the same code at startup, as shown in Figure 5.14, each processor then performs a series of initialization processes. The Fascicle Processor mainly loads its private data set, while the Monitor Processor loads public data, such as synaptic weights and routing tables, which is shared by all the Fascicle Processors (if there are more than one Fascicle Processors) on the same chip.
The timer on the Fascicle Processor is started after all other initialization processes (in both Fascicle and Monitor processors) complete, since the timer in-terrupt triggers the neuron state update, which requires all the data to be loaded.
To avoid conflict, a handshake procedure is introduced. When the Fascicle Pro-cessor finishes initialization, it sends a request to the Monitor ProPro-cessor to check whether the initialization process on the Monitor processor is finished. When
Code
Read SpiNNakerConfig file Read SpiNNakerConfig file
Setup Routing Table
Init SynapticWgts
Init Ethernet Init Interrupt Service Init Neuron Data
Init Lookup Table
Init Interrupt
Start Timer
Ready Ready
Ack Sleep
Fascicle Processor
Monitor Processor
Figure 5.14: The fascicle and monitor processors during initialization.
an acknowledgement from the Monitor Processor is received, the timer will be started. The Monitor Processor functions is very simple in this test. Users are able to develop more comprehensive applications for the Monitor Processor if necessary.
5.4.2 Downloading and dumping
The application code and neural data need to be downloaded to SpiNNaker chips to start the simulation. The semihosting functions provides by SoC designer allow user to access files on the hard disk of the Host PC directly, making the code and data downloading easy. To dump simulation results (spike raster, single neuron activity, and so on) is is also easy during the simulation. The output data is written to files on the Host PC and plotted in the Matlab.
5.4.3 A 60-neuron network test
Due to the limited speed of running the SoC Designer on a desktop computer, the system is initially tested by a small scale neural networks with a total of 60 random Izhikevich neurons. The ratio of excitatory neurons to inhibitory neurons is 4:1 – 48 excitatory neurons and 12 inhibitory neurons. Each excitatory neuron
Figure 5.15: A four chip simulation running on the SoC Designer simulator is randomly connected to 15 neurons, and each inhibitory neuron connects to 15 excitatory neurons, with a random delay of 0–15 ms. Among these neurons, 4 excitatory neurons and 1 inhibitory neuron are chosen as biased neurons, each receives a constant input current with an amplitude of 20 mV. The neural network data is converted by the InitLoad software with the “pre-defined network” option and downloaded to SpiNNaker chips with 15 neurons per fascicle processor.
Spike raster
Figure 5.15 shows the neural network being simulated in the SoC Designer Sim-ulator. Neuron states will be dumped to files on the hard disk of the host PC, using semihosting functions. The simulation runs for 1,000 ms.
In Figure 5.16, spike raster results generated from three different simulations are listed: Matlab simulation with floating-point arithmetic1 (Figure 5.16(a)), Matlab simulation with fixed-point arithmetic (Figure5.16(b)), and SpiNNaker simulation on SoC Designer (Figure 5.16(c)).
In Figure 5.16(c) neurons below the red line (at neuron ID 48) are excitatory and ones above the red line are inhibitory. The red lines at the bottom indicate the
1The Matlab code used in the rest of the thesis, is largely based on the code provided in [Izh06]
0 200 400 600 800 1000
Raster plot in Matlab (floating-point)
Neuron ID
Time (ms)
(a) Spike raster of the 60-neuron simulation on Matlab using floating-point arithmetic.
Raster plot in Matlab (fixed-point)
Neuron ID
Time (ms)
(b) Spike raster of the 60-neuron simulation on Matlab using fixed-point arithmetic.
(c) Spike raster of the 60-neuron simulation on SpiNNaker.
Figure 5.16: Spike raster generated from 60-neuron network simulations within 1,000 ms.
0 200 400 600 800 1000
(a) States of neuron 0 (excitatory)
0 200 400 600 800 1000
(b) States of neuron 3 (biased excitatory)
0 200 400 600 800 1000
Neuron States, ID = 50
Time (ms)
mV
electrical current membrane potential
(c) States of neuron 50 (inhibitory)
0 200 400 600 800 1000
40 Neuron States, ID = 54
Time (ms)
mV
electrical current membrane potential
(d) States of neuron 54 (biased inhibitory)
Figure 5.17: Neuron states and input currents from SpiNNaker simulation neuron firing rates at specific times. The biased neurons chosen are ID 3, 27, 36, 37 and 54. These neurons keep firing at all times and thereby trigger other neurons to fire (burst). There are fewer inhibitory neurons than excitatory neurons, but they are tuned to have higher firing rates. Since inhibitory neurons connect only to excitatory neurons, their firings shut down the bursting periodically.
Each of the three Figures in 5.16 clearly shows five bursts within the simulation time, corresponding to a rhythmic activity with a frequency of 5 Hz. There are reasonable differences between Figure 5.16(a) and Figure 5.16(b), caused by the differences between floating-point and fixed-point arithmetics. The spike timing in Figure 5.16(b) and Figure 5.16(c) is exactly identical – a strong demonstration of the functional correctness of the SpiNNaker model.
Single neuron activity
Figure 5.17 shows the membrane potential (red) and input current (blue) of several neurons from the SpiNNaker simulation. Here sub-figure 5.17(a) shows a normal excitatory neuron (ID 0) without biased input. It receives both excitatory and inhibitory inputs. Sub-figure 5.17(b) shows a biased excitatory neuron (ID
3) with a base input current of 20. It receives both excitatory and inhibitory inputs. Neuron 3 fires much more frequently than neuron 0 because of the biased input. Subfigure 5.17(c) shows a normal inhibitory neuron (ID 50) without biased input, which receives only excitatory inputs. Subfigure 5.17(d) shows a biased inhibitory neuron (ID 54) with a base input current of 20, which receives only excitatory inputs. As a result, neuron 54 fires more frequently than neuron 50. It is obvious that in this test inhibitory neurons fire more than excitatory neurons.
5.4.4 A 4000-neuron network test
Another test involves a simulation of a 4,000-neuron network (1,000 neurons per fascicle) with an excitatory-inhibitory ratio at 4:1. Each neuron is randomly con-nected to 26 other neurons. 72 excitatory and 18 inhibitory neurons are randomly chosen as biased neurons, each receiving a constant input stimulus of 20 mV.
The simulation results are compared between the floating-point arithmetic Mat-lab simulation (Figure 5.18(a)), fixed-point arithmetic MatMat-lab simulation (Figure 5.18(b)), and 4-chip SoC Designer based SpiNNaker simulation (Figure 5.18(c)).
The spike timings in the floating-point and fixed-point arithmetic Matlab sim-ulations are different, however, they show the same rhythm of 4Hz. The 4-chip SpiNNaker simulation matches the fixed-point arithmetic Matlab simulation. Fig-ure 5.19(a) shows the activity of an excitatory neuron (ID 0) and FigFig-ure 5.19(b) shows the activity of an inhibitory neuron (ID 3200), produced in the SpiNNaker simulation.
This test shows that the scale of the system can easily be increased when necessary. Each processor in a SpiNNaker chip is capable of modeling 1,000 neurons, indicating that to model a human brain with 100 billion (1011) neurons, it will require 5 million full SpiNNaker chips with 20 processors per chip and consume 2.3 MW to 3.6 MW (based on power estimation provided in [PFT+07]).