Simulation Results

Figure 6.5 The basic circuit diagram for echo cancellation.

6.3 S

R

The proposed design has been verified with Cadence SpectreRF and Verilog-A simulators. The transmission channel loss characteristic is based on an FR-4 material,

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which is the standard glass epoxy substrate. The transmission channel trace model is extracted from the Cadence Transmission Line Model Generator and is based on Reference [15] with approximately 1 dB of loss per inch at 10 GHz.

Figure 6.6 The simultaneous bidirectional PAM-4 transmission simulation results for the circuit of Figure 6.1.

Figure 6.6, part (1) shows simulation results for the signal loss in the channel versus the signal frequency at 2”, 4”, 6”, 8” and 10” lengths. Figure 6.6, parts (2)~(4) show the simultaneous bidirectional PAM-4 signaling transient simulation results at 5 Gbps for the circuit of Figure 6.1. Input and output signal eye-diagrams of the driver show how the 7-level characteristic on the transport channel arises due to the superposition from each end.

The transmission channel length used for the transient simulation in Figure 6.6 is 10

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inches and the driver input signals, VIR and VIL, are individual PAM-4 signals. Each of the PAM-4 signals is produced by a different pseudo-random-binary-sequence (PRBS) generator of length 2⁷ –1 bits.

Figure 6.7 The echo cancellation initialization setup simulation results for the circuits of Figure 6.1 and Figure 6.5

Figure 6.7 shows the echo cancellation initialization setup simulation results for the circuits of Figure 6.1 and Figure 6.5. The damping factor is set to be close to 0.707 for the tunable low-pass filter in echo cancellation so that the initialization time is optimized without stability concerns. The required initialization time is less than 2 uS after reaching a steady-state mode, as shown in Figure 6.7, part (1). The output of echo

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cancellation, as shown in Figure 6.7, parts (2) and (4), should be as small as possible in order to minimize the received signal degradation.

Figure 6.8 The adaptive channel pre-emphasis initialization setup simulation results for the circuit of Figure 6.3.

Figure 6.8 shows the adaptive channel pre-emphasis initialization setup simulation results for the circuit of Figure 6.3. The required initialization time is also less than 2 uS in order to reach a steady-state mode, as shown in Figure 6.8, parts (1) and (2). The transient signal amplitude at the data driver output increases as the pre-emphasis voltage increases, which maintains the same difference between driver current and pre-emphasis current so that the amplitude of the eye opening is kept constant, as shown in the other

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parts of the figure.

Figure 6.9 Simulation results for simultaneous bidirectional PAM-4 transmission with and without adaptive channel pre-emphasis after echo cancellation and pre-emphasis

have been initialized.

Figure 6.9 shows the simulation results for simultaneous bidirectional PAM-4 signaling with and without an adaptive channel emphasis after echo cancellation and pre-emphasis have been initialized. It shows that the adaptive channel pre-pre-emphasis helps to open the eye in the VER eye diagram, which improves the rise and fall times of the

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received signal.

6.4 C

This chapter presents a new design for a differential current-mode simultaneous bidirectional PAM-4 transmission system that uses BIST-based adaptive channel pre-emphasis. The BIST module compares the received signal against the known pattern sequence. The result of the comparison is an error bit indicator signal, which is fed back to the transmitter by utilizing the inherent feedback loop of the simultaneous bidirectional channel. In this way, it automatically adjusts the pre-emphasis to compensate for the actual channel loss characteristics. The proposed design has been verified using Cadence SpetreRF and Verilog-A simulators. The simulations show that the applied adaptive pre-emphasis greatly improves the quality of the link and therefore reduces the efforts needed to reliably recover the data at each receiver side.

R EFERENCES

[1] Genesys Logic America, Inc., “Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects,” Multi-Gigabit SerDes White Paper, Gensys Logic America, Inc., Sept. 15, 2003.

[2] The Serial ATA Working Group, “SATA 1.0a Specification,” The Serial ATA Working Group, http://www.serialata.org, Jan. 7, 2003.

[3] R. Drost, “Architecture and Design of a Simultaneously Bidirectional Single-ended High Speed Chip-to-Chip Interface,” Ph.D. Thesis, Stanford University, Palo Alto, CA, Nov. 2001.

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[4] D.N. de Araujo, M. Cases, and N. Pham, “Design Optimization Methodology for Simultaneous Bidirectional Interface,” IEEE Electrical Performance of Electronic Packaging, pp. 295-298, Oct. 2001.

[5] K.S. Canagasaby, S. Rajagopalan, and S. Dabral, “Interconnect Design Challenges in Source Synchronous Simultaneous Bidirectional Links,” IEEE Elect. Perf. of Electronic Packaging, pp. 11-14, Oct. 2002.

[6] R. Farjad-Rad et al, “A 0.3-μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver”

IEEE Jour. Solid-State Circuits, Vol.35, No.5, pp.757-764, May 2000.

[7] J. Sonntag et al. “An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25μm CMOS,” IEEE Custom Integrated Circuits Conference, pp.363-366, 2002.

[8] D. J.. Foley and M. P. Flynn “A low-power 8-PAM serial transceiver in 0.5- μm digital CMOS,” IEEE Journal of Solid-State Circuits, Vol.37, No.3, pp.310-316, March 2002.

[9] D.N. de Araujo, M. Cases, N. Pham, and D. Dreps, “Unidirectional vs.

Simultaneous Bidirectional Source Synchronous Signaling,” IEEE Electrical Perf.

of Electronic Packaging, pp. 7-10, Oct. 2002.

[10] M. Fukaishi, “GHz serial link transceiver using multiple-valued data representation,” IEEE 11th International Workshop on Post Binary ULSI, May 2002

[11] L. Harrison and H. Takatori, “Extending the Life of Today’s Backplanes through Simultaneous Bidirectional Transmission,” DesignCon 2004

[12] J. Zhang and Z. Wong, “White Paper on Transmit Pre-emphasis and Receive Equalization,” Mindspeed Technologies – A Conexant Bus., Oct. 2002.

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[13] K. Dalmia, “High Performance Backplane Design Using the Marvell AlaskaTM X Quad 3.125 Gb/s SERDES,” Marvell white paper, Nov. 2001.

[14] J.N. Babanezhad, “A 3.3 V analog Adaptive Line-Equalizer for Fast Ethernet Data Communication,” IEEE Custom Integrated Circuits Conference, pp. 343-346, May 1998.

[15] R. Kollipara, G Yeh, B. Chia, and M. Agarwal, “Design, Modeling and Characterization of High Speed Backplane Interconnect,” DesignCon 2003

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C HAPTER 7