Simulation validation

The simulation model was designed to evaluate the performance of the proposed voltage bal- ancing approach regarding the changes of the modulation index, sampling frequency, and the disable/enable transience. The parameters for the simulation model is shown in Table 13.

Table 13: The parameter used in the simulation to verify the proposed voltage balancing approach.

Parameters Values MMC power rating, 𝑃 (W) 100 DC-link voltage, Vdc (V) +/-50 Load resistance, 𝑅(Ω) 12.5 Load inductance, 𝐿(H) 0.001 Phase inductance, 𝐿𝑠(H) 0.001 Capacitance, 𝐶(F) 0.002

Submodule reference voltage, 𝑉𝑠𝑢𝑏(v) 25

No. of submodules in each arm, 𝑁 4

68

In order to match the simulation model with the experiment in future, the power rating was selected at 100w, which is the same as the experimental test rig. The voltage source at the DC side is +/- 50 V. The load and in-series inductors were selected at 1mH since it is within the range as calculated in Chapter 2.3. The selection of the capacitor is as the same as calculated in Chapter 2.3. The number of the submodule was four, so that it will generate five voltage steps with the mid-point located at the zero voltage.

V

R

V

L

L

1

_

2

2

_

1

V

L

V

V

V

V

Figure 34: The simulation model of the single phase MMC.

The model was built based on the structure shown in Figure 34. In both upper and lower arms, there are four submodules. Since they are connected in series, the current flowing into the submodule is either zero or the same as the arm currents. The capacitor voltage for the up- per arm are measured as 𝑉_{𝑐_𝑢𝑝1}…𝑉_{𝑐_𝑢𝑝𝑛}, for the lower arm are measured as 𝑉_{𝑐_𝑙𝑜𝑤1}…𝑉_{𝑐_𝑢𝑝𝑛}. The difference voltage generated by the imbalanced capacitor voltage for the upper and lower arms are 𝑉_{𝑑𝑖𝑓𝑓_𝑢𝑝} and 𝑉_{𝑑𝑖𝑓𝑓_𝑙𝑜𝑤} separately. The upper and lower arm current are 𝐼_𝑢𝑝 and 𝐼_𝑙𝑜𝑤. The output voltage and current are 𝐼𝑜𝑢𝑡 and 𝑉𝑜𝑢𝑡 respectively. As shown in Figure 34, the

measured signals, such as 𝑉_{𝑐_𝑢𝑝1}…𝑉_{𝑐_𝑢𝑝𝑛}, 𝑉_{𝑐_𝑙𝑜𝑤1}…𝑉_{𝑐_𝑢𝑝𝑛} are transmitted in to the FPGA. Therefore, the primary control signals, such are generated to produce the gate signals. In the Simulink model, the FPGA is represented by several control blocks in order to perform the calculation.

69

Figure 35: The converter (a) upper and lower arm currents (b) the current output (c) upper and lower arm capacitor voltages (d) voltage output when the sampling frequency is insufficient.

To test the feasibility and the dynamic performance of the proposed voltage balancing con- trol, a single-phase MMC based inverter has been built in MATLAB. The model is running in the discrete mode with 1𝑢𝑠 time steps since the maximum frequency in the HVDC simulation model is 1 kHz, which has a minimum time step of 1𝑚𝑠. Running in discrete mode with 1𝑢𝑠 time steps guarantees the accuracy of the system which is 1% of the minimum time steps and the simulation time required is also significantly reduced.

Described in Figure 35, in the same sampling frequency condition where the samples taken are insufficient, the proposed predictive voltage balancing control can still maintain the capac- itor voltages at the nominated level with fewer variations than the original voltage balancing control. When the proposed voltage balancing control is activated at 0.25s, the upper and lower arm current shown in Figure 35 (a) contains a significant amount of circulating current

----upper current

----lower current

----upper capacitor ---lower capacitor

----upper capacitor ---lower capacitor

----upper capacitor ---lower capacitor

----upper capacitor ---lower capacitor

----output voltage

70

with the peak value increasing from 7.2A to 19.5A (170.8%). However, as expected, the cir- culating currents have limited effects on the converter output current as displayed in Figure 35 (b). The deviation of the upper and lower arm capacitor voltages are shown in Figure 35 (c) before 0.25s when the sampling frequency is low. As observed in Figure 35 (d), the converter output voltages can return to steady states when the proposed voltage balancing is activated after 0.25s.

Figure 36: The voltage balancing is disabled at 0.2s and enabled again at 0.25s (a) upper and lower arm current (b) upper arm capacitor voltages (c) lower arm capacitor voltages (d) load

voltage and reference signals

The voltage balancing control is disabled at 0.2s and enabled again at 0.25s as shown in Figure 36,When the voltage balancing is disabled, the capacitor voltage deviations are ob- served in both of the upper and lower arm as shown in Figure 36 (b) and Figure 36 (c). The upper and lower arm currents are affected by the imbalanced upper and lower arm capacitor

----upper current ----lower current ----upper capacitor ----upper capacitor ----upper capacitor ----upper capacitor ----output voltage ----reference signal ---lower capacitor ---lower capacitor ---lower capacitor ---lower capacitor

71

voltage as well. As shown in Figure 36 (a), they generated 400% more ripple when the volt- age balancing is disabled, although the upper and lower currents magnitudes have changed by nearly five times. The output waveform has not changed significantly as shown in Figure 36 (d), and only a small ripple is observed. In combination with (1)-(4), the 𝐼_𝑝 and 𝐼_𝑛 have not changed much, further indicating that the circulating current existing inside the converter is generated by the capacitor voltage imbalance and it has limited effect on the output wave- form.

Figure 37: The simulation results (a) the upper and lower arm current (b) the load current (c) upper and the lower arm capacitor voltages (d) load voltage with reference signal when the

modulation index changes from 0.5 to 0.95 at 0.25s

The modulation index was changed from 0.5 to 0.95 at 0.25s as demonstrated in Figure 37 to test the dynamic performance of the proposed control. It can be seen that in Figure 37 (a), the upper arm current and the lower arm current are acting as the positive and negative halves of a sinusoidal waveform, and which are forming the converter output current as shown in Figure 37 (b). However, the harmonics displayed in Figure 37 (a) are generated by the circu-

----upper current ----lower current ----output voltage ----reference signal ---upper capacitor ---lower capacitor

72

lating current existing at twice the fundamental frequency. The control of the circulating cur- rents is not included. As shown in Figure 37 (c) the upper and lower arm capacitor voltages are balanced within a certain range from 25.7v to 24.7v whereas the nominal voltage is 25v, the voltage variation is 2.8% which is within the variation range agreed by the grid codes. However, the performance and the voltage variation ranges are different according to the volt- age level of the application. The output voltage as shown in Figure 37 (d) has five voltage steps when the four submodules in each arm are fully activated. Before 0.2s, there are only three voltage levels as the modulation index is only 0.5 and only two submodules are turned on at the same time. By integrating a large number of the submodules, the voltage steps are relatively small. Furthermore, because of the characteristics of the MMC, it is easier to in- crease the number of converter voltage levels compared to the other types of conventional converters. Figure 37 demonstrates that the proposed predictive voltage balancing control has a fast system response regarding the modulation changes as it can reach the steady states within one operation cycle.