Single phase block diagram

We will begin by introducing a block diagram for a single phase of the controller, Fig- ure 6.14, and briefly discuss each component. This diagram identifies how the compo- nents interconnect, useful for the full system specification.

Initially, it can be seen in this block diagram that there are two clear sections,

Activation and Charging, which are connected by a handshake. We will discuss each

section individually.

Activation section

• HL_WAIT (High-load WAIT) - This is a WAIT element, which will be discussed

in Section 6.2.2. hl is a non-persistent analogue signal and thus cannot be used

directly as an input to an asynchronous digital circuit. The WAIT element serves

to sanitize this analogue signal, setting the digital signal sanhigh whenhlcrosses

the threshold indicating it is high, signalling the high-load condition.

• HLH (High-load handler) A.1 - As the high-load condition sets all phases to charge,

this will take the hl signal (sanitized by HL_WAIT), and then request that this

phase, and all phases, activate, and set the charging section into charge mode, switching the PMOS transistor ON and the NMOS transistor OFF.

• TC (Token control)A.2 - This takes a token from the previous phase, via get,

which will then send a request to the merge element, which in turn will activate the charging section. The TC will also simultaneously send a request to the TOKEN_TIMER, which will ensure that the token is kept in this phase for a

Figur e 6.14: Block diagram of a single phase of the contr oller [1]

minimum amount of time. When the activation section is complete, the TC will receive an acknowledge, and when both this and the acknowledge from the TOKEN_TIMER are received, it will pass the token to the next phase, via the

pass signal.

• TOKEN_TIMER (Delay) A.3 - The token timer is started as the token is received

from get in order to delay the token being passed to the next phase via pass.

Delays are used multiple times throughout a phase, and each operate in the same way to provide a delay.

• MERGE A.4 - This MERGE element aims to combine the request and acknowledge handshakes from HLH and TC, both of which aim to activate the phase, into one channel, which is passed to the charging section to activate it. This was, whether the circuit is in high-load condition, or the token is passed, the charging section will be activated.

The operation overview of the activation section is: Either a token will arrive at this phase, or the high-load condition will signal. Either or both of HLH or TC will send requests to MERGE, which will send a request to the charging section from one of these. When the acknowledge signal comes from the charging section, MERGE will send the acknowledge to one of HLH or TC, depending on which device sent the original

request. If HLH receives the acknowledge, then this will remove the latched hl signal

from the WAIT element, resetting it. When TC receives an acknowledge, it synchronises with the acknowledge from the delay, which indicates it has been a minimum length of time to hold the token, and then passes the token to the next phase.

Charging section

• UV_WAIT (Under-voltage WAIT) - A WAIT element (Section 6.2.2). uvis a non-

persistant signal, similar to hl and must be sanitized to be used with the digital

circuit. The output of this, sanwill then signal the under-voltage condition if uv

is deemed to be high.

• UVH (Under-voltage handler) A.5 - When the activation section sends a request, this then checks the UV_WAIT for the under-voltage condition. If this is signalled, then the acknowledgement is sent back to the activation section, so this can then

pass the token to the next phase (ai), and it sets the output request ro high, sending it to the ZCH module.

• ZCH (Zero-crossing handler) A.6 - zc may not signal, or it may signal after the

request comes from UVH viari. In either of these cases, the condition is ignored.

zcmay go high before any request comes from UVH however, and in this case the

request,ro will go high, which is passed to OCH to switch both power regulating

transistors OFF. When ri goes high, which signals that uv has gone high, this

will then set ro low, to switch ON the PMOS transistor to fix the under-voltage

condition.

• OCH (Over-current handler) A.7 - This component controls the switching of the

transistors. The request from ZCH, viari determines the switching of transistors.

Whenrigoes high, the NMOS transistor is switched OFF, and whenrigoes low,

the PMOS transistor is switched ON. When the over-current condition is signalled byoc, then this will switch the transistors in the opposite way.

• PMIN_DC (Delay control for PMOS) A.8 - This component is used to switch the PMOS transistor ON for a minimum period of time. The request comes from OCH

when it sets rp high, for ri to PMIN_DC. This will set ro high, to switch the

PMOS transistor ON, and set rd high to start the delay (PMIN_TIMER). When

the transistor is acknowledged as being switched ON bygp_ackand the timer has

completed, signalled by ad, only then can the acknowledge be sent back to OCH.

• PMIN_TIMER (Delay) A.3 - When rd is set high from PMIN_DC this then will

set ad high after a delay, the minimum period of time the PMOS transistor can

be switched ON for.

• NMIN_DC (Delay control for NMOS) A.8 - This is the same as PMOS_DC, but

switches the NMOS transistor according to the requests from the rn signal from

OCH. It uses NMIN_TIMER to switch the NMOS transistor ON for a minimum period of time.

• NMIN_TIMER (Delay) A.3 - Similar to PMIN_TIMER, this will allow the NMOS transistor to be switched ON for a minimum period of time.

The operation overview of the charging section is: When a request comes from the activation section, UVH will then check for under-voltage. When this signals, it sends

a request to ZCH. This can either pass the request straight to OCH, switching the NMOS transistor OFF and the PMOS transistor ON, if zero-crossing either signals after under-voltage, or does not signal at all. If it signals before under-voltage, then it sends a request to OCH to switch the NMOS transistor OFF, but waits for a request from UVH before removing the request, which switches the PMOS transistor ON.

OCH will switch the signals as requested from ZCH, but if the over-current condition is signalled, then it switches the PMOS transistor OFF and the NMOS transistor ON.

OCH uses request signalsrpto switch the PMOS transistor, andrnto switch the NMOS

transistor. These signals are received by PMIN_DC and NMIN_DC respectively, which will switch the transistors according to the requests. If being switched ON, then a delay is used to ensure that the transistors are ON for a minimum length of time.