Sizing the drive system
4.3 Sizing the power electronics
All of the electrical power directed to the hybrid propulsion M/G must pass through the power electronics. It has been said that control electronics uses power to process information and that power electronics uses information to process power. In this section we describe how power electronics is sized to match the electric machine to the vehicle energy storage system, via information processed by the control electronics.
Figure 4.13 is a schematic for the hybrid propulsion system ac drive system con-sisting of on board energy storage, power processing according to control algorithms, and traction actuation via the M/G and vehicle driveline.
The essentials of ac drive system operation are that power from a dc source such as a fuel cell, battery or ultra-capacitor is converted to variable voltage, variable frequency ac power at the M/G terminals, Vφ and Iφ. The M/G then converts this electrical power to mechanical power in the form of torque and speed at the trans-mission input shaft, T and ω. The power electronics is an electrical matching element in much the same manner that a gearbox processes mechanical power to match the
Vb Ri
Rd
Vφ, Iφ
T ω
Controller, comm.
gate drives, pwr supply C'mds
Power electronics
Control electronics
Transmission
Driveline
Figure 4.13 Schematic of hybrid ac drive system
Vsystem for Isys = 250 A Conductor size according to
1996NEC, no more than 3 cond bundle, <90°C
Figure 4.14 Power throughput capability versus voltage (a) and required cable sizes (b)
engine to the road load requirements. The power inverter matches the dc source to the mechanical system regardless of torque or speed level, provided these quantities are within its capability.
The power processing capability of power inverters is directly related to the dc input voltage available. Higher voltage means more throughput power for the same gauge wiring and semiconductor die area. Figure 4.14 captures the power throughput versus voltage given the system constraint on current of 250 A due in part to cable size, connector sizes and contactor requirements. The reader will appreciate that practical
contactors rated in excess of 250 Adc interruption capability are far too bulky and expensive for hybrid vehicle applications. In the case of battery EVs, contactors using high energy permanent magnet arc suppression are used effectively to 500 Adc. In Figure 4.14(a) notice that as automotive voltages move to 42 V PowerNet the sustainable power levels will approach 10 kW. For hybrid propulsion the chart illustrates the recommendation that voltages in excess of 150 V are advisable. With recent advances in power semiconductors there is ample reason to move to voltages beyond 300 V provided the energy storage system does not suffer and complexity is manageable.
Figure 4.14(b) reveals that recent hybrid propulsion systems cluster along the 100 A trend line with the exception of the new Ford Escape (200 A) and the GM EV1 (not shown). At distribution voltages above 600 V special precautions must be taken, such as rigid conduit. For distribution currents higher than 250 A the contactor necessary to galvanically isolate the battery becomes excessively bulky.
4.3.1 Switch technology selection
Power electronic switching components are classified by process technology as orig-inating from two layer, three layer or four layer designs. The semiconductor diode, for example, is a two layer planar device consisting of p-type and n-type doped silicon formed by a diffusion process. Two layer devices have a single p-n junc-tion. Three layer planar devices include all the transistors in use today and have two junctions. Current control is realised at the low voltage junction at which car-riers are injected into the device and output at a second, higher voltage, junction at which the injected carriers are collected. Because of the vast difference in voltage levels between the injecting and collecting junctions, for a given amount of current, high power amplification occurs. Four layer, three junction, devices are categorised as thyristors. ‘Thyristor’ is a name derived from early work on gas tube Thyratron switching elements at the General Electric company in the 1920s that is taken from the Greek – ‘thyra’ for door and ‘tron’ for tool. Thyristors are then ‘thyratrons’ plus
‘transistors’. Because there are two junctions from which carriers are injected in thyristors, and a single high voltage collector junction, the devices have a tendency to latch-up due to current injection at the 3rd junction unless some effort is expended in forcing the current gain of this junction to be low enough to inhibit latch-up.
The volt-amp capability of available power semiconductor switching devices is summarised in Figure 4.15 to contrast their power handling capability with switching frequency capability. Device terminology is explained in Table 4.7 on page 133, including inventorship and year introduced.
4.3.2 kVA/kW and power factor
In this section the key aspects of power semiconductors will be introduced and the rela-tionship of V-A apparent power based on device ratings versus real power throughput.
Virtually all power electronics inverters for hybrid propulsion employ IGBT device
Power capability, kVA
Figure 4.15 VA versus frequency capability of power semiconductors
E
Figure 4.16 Illustration of non-punch-through and punch-through IGBTs
technology. There has been some misconception regarding this technology, particu-larly in terms of what is a ‘motor-drive’ IGBT. This section will address that concern.
Power semiconductor devices range in voltage withstand capability of from 3 kW to 6.5 kV and current magnitudes of 3 to 4.5 kA. Thyristors have the high-est kVA ratings, but are generally slow switching. The gate turn off thyristor, GTO, is capable of switching 3 kA at 4.5 kV but is limited to less than 700 Hz. The emitter turn off thyristor, ETO, is capable of simultaneously switching 4 kA at 4.5 kVA at relatively high frequency. IGBTs are making enormous progress in both voltage and current ratings, with some IGBT introductions being capable of 6.5 kV and 3.5 kA (not simultaneously), and high frequency versions are capable of processing kWs at switching speeds of up to 100 kHz (e.g. ultra-thin IGBTs).
Figure 4.16 is a cross-section of the two principal varieties of IGBTs, the punch-through, PT, and non-punch-punch-through, NPT, device structure [6,7].
Table 4.6 Insulated gate bipolar transistors for hybrid propulsion application
Non-punch-through, NPT Punch-through, PT
Wafer process, starting material∼85 μm
to 170μm Epitaxial process∼50 μm on wafer
360–800μm Variously called: DMOS-IGBT,
homogeneous, or ‘motor-drive’ IGBT because of DMOS switching behaviour
Planar IGBT or epi-type
Triangular electric-field device, emitter to n−base
Trapezoidal electric-field device, emitter to buried n+layer
Higher Vce(sat), low Esw Low Vce(sat), high Esw, difficult to parallel
Higher carrier lifetime, no lifetime control necessary
Low carrier lifetime through
electron-irradiation or ion implant for lifetime control
Wafer cost is 25% to 40% cost of epi-type Expensive device, approx. 2.5× NPT cost
The essential distinction between a ‘motor-drive’ IGBT, e.g. the NPT structure, is whether the device is manufactured using wafer processing in terms of dopant diffusion from both sides or whether the device is manufactured using integrated circuit processes of growing an epitaxial layer onto a wafer and then processing using planar techniques. The two processes are listed in Table 4.6 for a side-by-side comparison.
Table 4.7 lists the major power semiconductor devices, their accepted schematic symbol, and various details regarding development and market introduction.
4.3.3 Ripple capacitor design
Power electronic inverters may have as much as 60% of their volume taken by the dc link capacitors needed for bypassing the load ripple currents. The dc bus capacitor is sized not so much for energy or hold up time, but thermally by the rms ripple current it must circulate. First-principle understanding of inverters states that no energy storage occurs in the inverter, only switching elements. However, the high frequency currents generated by the inverter switching are sourced by the dc link capacitor, particularly if the battery is located far from the inverter. In hybrid propulsion systems when the inverter is required to be packaged within 1 m of the M/G to minimise EMI, it is the bus capacitors that source and sink the switching frequency components.
The battery in effect keeps the capacitor bank charged by supplying the real power demand.
Electric motor current is synthesised from the dc line voltage through a modulation process. The inverter is essentially a class D amplifier controlled to modulation depths necessary to create the fundamental component at the output. A rule of thumb for sinusoidal ac drives is that the bus capacitors must be rated for 60% of the M/G
Table 4.7 Power semiconductor evolution
1948 Bell Labs RCA, others
G G
S S
D D
FET Junction field effect transistor
1952 Bell Labs RCA, others
A
TRIAC Triode ac switch 1965 GE GE
S
Table 4.7 Continued
NCSU: North Carolina State University; PSRC: Power Semiconductor Research Center
phase current. For example, if the hybrid propulsion system M/G is rated 200 Arms, then the ripple capacitor bank must be capable of sinking 120 Armsof ripple current at the inverter switching frequency, fs. Since fs ranges from 5 kHz to over 20 kHz in production traction inverters, the capacitor bank must be sized to sink this much current continuously and remain within its thermal constraints.
Electrolytic bus capacitors with organic electrolytes are restricted to operation at 85◦C or less. It is true that aluminium electrolytics have temperature ratings of 105◦C to as high as 125◦C, but these are not continuous ratings. Multilayer polymer, MLP, type capacitors1 are stable over temperature, resilient under thermal shock, stable over mechanical stress such as mounting stress, and have ultra-low ESR. It is this term, equivalent series resistance, ESR, that distinguishes a bus capacitor for ripple current bypassing from a dc link hold-up capacitor for energy storage, such as in an uninterruptible power supply. The ESR of a capacitor is a strong function of operating temperature and frequency of the ripple current.
The dc link capacitor ESR model consists of a bulk capacitance component (capac-itance of the etched foil area, A, and electrolyte gap, d, where C= εA/d), the dielectric loss capacitance modelled as a capacitor value in parallel with a resistance, and the series combination of electrolyte and foil resistances. Figure 4.17 is the ESR
1 ITW Paktron, www.paktron.com, manufacturer of multiplayer polymer MLP capacitors for use in power electronic converters and inverters. MLP style capacitors outperform ceramic, MLC style.
Cb
Cd
Rd
Re Rf
Rated capacitance
Dielectric loss components
Resistance of electrolyte Resistance of foil + current collectors
Figure 4.17 Dc link capacitor ESR model
ESR Xc
δe θe
De=1/Qe = tan(δe) PF = sin(δe) = cos(θe)
Figure 4.18 Construct for dc link capacitor dissipation factor from ESR
model currently in use by researchers to characterise losses in the inverter dc link capacitor bank [8].
An equivalent series inductance would also be added in series in the ESR model for a more realistic complete equivalent. The equivalent series inductance of a film capacitor (EC35μF, 500 V) is 35 nH. For the ESR model shown, the dielectric loss time constant, τd = RdCdis taken as 20 times the capacitor bulk capacitance times series resistance time constant in order to model the dielectric loss factor. For a 470μF ceramic dielectric capacitor, the electric dissipation factor, De, or, equivalently, the tangent of the loss angle, is equal to 0.036 at 100 Hz. Figure 4.18 illustrates the definition of the loss tangent.
The capacitor loss factor is a measure of deviation from ideal capacitive reactance caused by the presence of ESR. Equation (4.6) summarises the definition of dissipa-tion factor, or loss angle, in terms of the capacitor’s conductivity, permittivity and
frequency:
De= 1
Qe = tan δe = tan(90◦− θe)= σ ωε PFe= sin δe= cos θe= De
(1+ De2) (4.6)
For the ceramic capacitor example, the internal ESR is 0.122 at 100 Hz. If we further assign values of 6 m and 23 m to the electrolyte and foil resistances we obtain a total package ESR= 151 m. From these data the capacitor has an inherent time constant, τc = ESR C = 0.151 × 470 × 10−6 = 71 μs. Using the empirical relation stated above, we assign a dielectric time constant τd = 20τc= 1.46 ms, from which the dielectric capacitor value, Cd, computes to 12 000μF. These data are then put in the model shown in Figure 4.18 and the ESR solved as a function of frequency using the empirical relation given in (4.7) [8]:
ESR= Rd
(1+ ω2τd2)+ Ree−
(Tc−Tb)
se + Rf (4.7)
Here the sensitivity of electrolyte with temperature is taken as se= 5. When this capacitor is simulated over the normal motor drive frequency range of 100 Hz base frequency to 5 kHz switching frequency the plot shown in Figure 4.19 results.
The variation in ESR with frequency in Figure 4.19 is calculated when the capac-itor case temperature is held at 60◦C by the inverter cold plate and assuming the core temperature is at 85◦C. The frequency knee in Figure 4.19 is given by the dielectric loss model parameters, τd.
A novel technique with proven ripple current magnitude reduction is described in Reference 9 wherein the currents to a 6-phase induction machine are shown regulated by dual inverters, each rated 50% of the machine throughput power, and having their current regulators phase shifted such that the resulting dc link capacitor currents are halved in magnitude but doubled in frequency. Since capacitor heating is proportional
ESR(f)
f
1000 2000 3000 4000 5000
0 0.05 0.1 0.15
Frequency, Hz BaTiO ceramic capacitor ESR
ESR, Ohms
Figure 4.19 ESR variation with frequency for the model in Fig. 4.17
to magnitude squared, this technique offers an opportunity to further reduce ripple capacitor size.
The model for ESR is used in an inverter simulation to account for losses in the capacitor bank due to ripple currents from the inverter. The next section presents an illustration of inverter PWM operation and its contribution to capacitor bank ripple currents.
4.3.4 Switching frequency and PWM
The example used in this section and shown in Figure 4.13 will be assumed to be driving an IM automotive starter alternator in boost mode. In this scenario, the IM ISA will be operating at 8 kW of boost during a lane change manoeuvre. The vehicle power supply will be a 42 V advanced battery with an internal resistance of 37 m resulting in an inverter terminal voltage of 33 V. For these conditions the dc link current will be 242 Adc. The inverter in this example uses sine-triangle ramp comparison in the current regulator to synthesise the output phase voltage. Equation (4.8) gives the fundamental ISA motor phase voltage for modulation depth m, 0 < m < 1:
Vph1= m
πVdsin(ωbt ) (Vrms) (4.8)
where Vd is the dc link voltage. For a 42 V battery under load, (4.8) predicts a peak phase voltage of 14.85 V. For the stated conditions the ISA phase current will be
Iph1=
√2Pe
3Vph1 (Arms) (4.9)
This calculates a 254 Armsphase current into the ISA for the case of 8 kW power level in boosting at 2400 rpm at the engine. For a 10-pole ISA the fundamental frequency will be f = 200 Hz, as given by (4.10):
f = P n
120 (Hz) (4.10)
For this example, ramp comparison (also, sine-triangle) modulation will be used in the inverter controller to generate the inverter bridge switching waveforms. Ramp comparison is a technique of encoding an analog signal, in this case the motor phase voltage at its base frequency of 200 Hz, into digital pulses that are applied to the power semiconductor gates. Inverter current will then flow into or out of the motor according to which switches in a six switch inverter are activated. Figure 4.20 gives a schematic of the inverter switch arrangement, the controller and load as well as the control signal generation.
The process of generating digital switch waveforms representing the magnitude of an analog controlling signal is pulse width modulation. Figure 4.20 illustrates the case of modulation depth m = 0.80 showing how the switch conduction periods (state 1) versus its off periods (state 0) are defined.
Vb Ri
Rd
Controller, comm.
gate drives, pwr supply C'mds
Power electronics
Control electronics
Vφ, Iφ
Inverter schematic for hybrid ISA system (a)
Inverter controller ramp-camparison modulator (b)
0 0.001 0.002 x 0.003 0.004 0.005
–5 0 5
G(x) fb(x)
0 0.001 0.002 x 0.003 0.004 0.005
–1 0 1
Digital control waveforms for inverter phase A (c)
fs(x)
Hybrid M/G phase A switch current (d )
Ia(x)
0 0.001 0.002 x 0.003 0.004 0.005
–1 0 1
T
ω Transmission Driveline
Figure 4.20 Power inverter PWM
In Figure 4.20 the corresponding phase A current is plotted over one cycle. During the positive portion of Ia(x)the switch current is shown occurring for the duration of the switch on time. The negative current in phase A represents diode conduction.
Capacitor ripple current is the summation of Ia(x)+ Ib(x)+ Ic(x)and consists of pulses as shown in Figure 4.20(d).