The use of SnS absorber material in solar cells started 30 years ago, when Sharon and Basavaswaran in 1988 [96], observed the PV potential of SnS in photo-electrochemical (PEC) cell exhibiting a photo conversion efficiency of 0.63% with the structure SnS/Ce4+, Ce3+/Pt.
SnS solar absorbers were grown by passing H2S through an acidic solution of stannous
chloride (SnCl2). Other SnS absorbers synthesised by different chemical routes used in PEC
cells show similar PV characteristics of > 0.50% conversion efficiency with fill factor >0.6 [97]. Research towards using vacuum evaporated SnS absorbers in solar cells started in 1994,
38
Noguchi et al. [36] successfully synthesised SnS absorber using thermal evaporation technique and produced ITO/n-CdS/p-SnS/Ag cell structure. It showed an open circuit voltage (Voc) of 120 mV, a short circuit current density (Jsc) of 7 mAcm-2, a fill factor (FF) of 35% and conversion efficiency () of 0.29%. This work appeared to have spurred the research interest of PV community into SnS material with Reddy et al 1997 [37] fabricating Al/n-CdS/p-SnS/Ag device structure with a Jsc and of 8.4 mAcm-2 and 0.5%, respectively. SnS-based solar cells can be fabricated in the substrate or superstrate configurations. Figure 2.5 shows the schematic illustration of a typical SnS solar cell in substrate and superstrate configuration.
Figure 2.5. Schematic illustration of substrate and superstrate configurations for a typical SnS solar cell.
Generally for the substrate configuration, there is the glass substrate, the metallic back contact (normally Mo or Cu), the absorber layer (p-type), the buffer layer (n-type), the transparent conducting oxide (e.g i-ZnO/ITO) and metal front contact (e.g Ni/Al). The stacking sequence is glass/Mo/p-SnS/n-ZnS/i-ZnO/ITO/Ni-Al and the illumination takes place through the front contact. The first-ever produced SnS-based working device was in substrate configuration with power conversion efficiency of 0.63% [96], this was followed by Reddy et al. in 2006 [47] synthesised SnS onto glass/SnO2 substrate via chemical spray pyrolysis. Reddy et al. coated
the SnS absorber with evaporated indium doped (CdS:In) buffer layer (p-SnS/n-CdS junction) before finally depositing a 400 nm thick indium to form the top contact. The best cell exhibited
Glass- substrate
Mo- back contact SnS- absorber layer
ZnS- buffer layer ZnO/ITO- window layer
Ni/Al contact grid
Glass- substrate ITO- front contact
SnS- absorber layer ZnS- buffer layer Illumination G row th order Gr ow th orde r
(a) Substrate configuration (b) Superstrate configuration
39
an open circuit voltage of 260 mV, a short circuit current of 9.6 mAcm-2, a fill factor of 53% and
efficiency of 1.3%. The best efficiency reported so far on p-SnS/n-CdS in substrate configuration is 2.53% via thermal evaporation of SnS absorber [98]. The substrate configuration further progressed with the use of alternative wider bandgap buffer layers to replace CdS. Recently Reddy et al in 2015 achieved an improved efficiency of 2.02% by replacing CdS with ZnMgO using the configuration of Mo/SnS/Zn0.76Mg0.24O/ZnO:Al/Ag [99].
Other J-V characteristics reported are Voc = 575 mV, Jsc = 9.96 mAcm-2 and FF = 36.4%, they attributed high Voc to the reduction in the recombination due to low Jsc. They synthesised the SnS absorber by sulphurisation of sputtered Sn precursor layers in a closed chamber, while the Zn0.76Mg0.24O buffer layer was grown by chemical spray pyrolysis. Power conversion
efficiencies of over 2% was reported via modifications in device design (Mo/SnS/Zn(O,S)/ZnO/ITO), post deposition heat treatments and optimisation of p- absorber/n-buffer band alignments via tuning of the conduction band offset (CBO) [100, 101]. This efficiency was nearly doubled by adding thin layer of SnO2 (1nm) at SnS/Zn(O,S)
interface, reaching efficiency of 3.88% as reported for SnS deposited via congruent thermal evaporation [102] and world record efficiency of 4.4% [28] for SnS synthesised via atomic layer deposition (ALD). This record efficiency device exhibited Voc, Jsc and FF of 372 mV, 20.2 mAcm-2 and 58.0%, respectively in a cell area of 0.232 cm2. This high efficiency device
was achieved following the annealing of SnS layer in H2S to enlarge grains and reduce
recombination loss at grain boundaries and oxidizing SnS surface before junction formation to suppress recombination centre losses to the junction.
On the other hand, superstrate configuration is fabricated in a reverse order compared to substrate configuration (see figure 2.5b) in the following stacking sequence: glass substrate/front contact/n-ZnS/p-SnS/metal back contact. Note that front contact can be indium tin oxide (ITO), fluorine-doped tin oxide (FTO) or aluminium zinc oxide (AZO). The n-buffer layer can be zinc sulphide (ZnS), cadmium sulphide (CdS), indium sulphide (In2S3) or zinc
40
molybdenum (Mo). Research into fabrication of SnS-based solar cell in superstrate configuration started in 1994 when Noguchi et al. [36] produced an ITO/CdS/SnS/Ag structure. The SnS absorber was deposited via vacuum evaporation method, best cell exhibited an open circuit voltage of 120 mV, a short circuit current density of 7 mAcm-2, a fill factor of 35% and a
conversion efficiency of 0.29%. Reddy et al in 1995 reproduced same structure but replaced ITO with aluminium using spray pyrolysis method to synthesis SnS absorber and vacuum evaporated CdS. They produced an improved current-voltage properties as follows: Voc = 140 mV, Jsc = 8.4 mAcm-2, FF = 38% and = 0.5% [37]. An attempt in 2009 by Ghost et al. to fabricate SnS in superstrate configuration by thermally evaporating SnS onto ZnO buffer layer resulted in inefficient device [103]. The glass/ITO/ZnO/SnS/In structure used exhibited Voc,
Jsc, FF and of 120 mV, 0.04 mA, 33% and 0.003%, respectively in a cell area of 0.4 cm2. Following this, efficiency of SnS solar cells in superstrate configuration stagnated until recently in 2013 Schneikart et al. fabricated a CdS/SnS heterojunction device via thermal evaporation of the SnS absorber [104]. The best device exhibited an open circuit voltage of 217 mV, a short circuit current of 19.0 mAcm-2, a fill factor of 39.2% and a power conversion efficiency of
1.6%. They attributed the low open circuit voltage to possible existence of pinholes in the SnS layer and the cliff at the CdS/SnS interface. Similar to the substrate configuration, replacing the CdS layer with wider bandgap material may be the way forward. Ikuno et al in 2013 [105] further improved the power conversion efficiency of SnS device in superstrate configuration to 2.1% by replacing CdS with wider bandgap buffer layer material of Zn1-xMgxO to optimise the CBO and post fabrication annealing. The device also exhibited Voc , Jsc and FF of 270 mV, 12.1 mAcm-2 and 64%, respectively. They attributed the improvement to mainly conduction
band offset optimisation.
From the literature, it is evident that each of the different layer components that make up a working device can affect the performance of the solar cells. As their properties differ in microcrystalline structure, carrier mobility and optical bandgap, there are bound to be, recombination centres, inter diffusion, chemical changes, defects and interface states that can
41
result in electrical and optoelectronic changes [106]. Therefore, the properties of materials used for these layers should be investigated before their application in solar cells.