SPLE specification of the Delay block

In the same setting as for the MinMax block SPLE specification, we provide here the one for the Delay block. We provide in Figure 5.42 a feature model for its specification.

Figure 5.42: A feature model for the Delay block structure and semantics

The root element of Figure 5.42 is the product line itself. It is named after the block (DelayBlock) (REQ- 1.a). Beneath the root element, we provide all the mandatory features and their children features below. Structural features

The structuralFeatures feature is a mandatory abstract feature holding all the variable structural fea- tures of the block specification (REQ-2.a, REQ-3.a, REQ-4.a):

• inputs_outputs: a mandatory abstract feature holding the specification for the inputs and out- puts ports of the block.

– v_output: the output port of the block – u_input: the input data port of the block

5.5. SPLE FOR THE SPECIFICATION OF BLOCKS

• initial_condition: a mandatory abstract feature holding an alternative relation between two features: ic_input and ic_parameter. These two features represent the two possible configura- tions for providing the initial condition for the block, either dynamically as an input signal or stat- ically as a parameter. Both variants are abstracts and contain alternative sub-features modeling the scalar or vector dimension of the initial_condition. It is mandatory for the initial_condition to be either scalar or vector as it is mandatory to store multiple values in it for a delay parameter value (N) greater than one.

• ic_mode_parameter: a mandatory feature modeling a parameter holding the choice between the dynamic or static way of providing the initial_condition value.

• delay_parameter: a mandatory abstract feature representing the previously specified N value. • resettable: an optional abstract feature holding the res_input optional feature representing

the reset input port and a mandatory parameter reset_algo indicating which algorithm is used to activate the reset according to the res_input input signal value as defined in Section 5.2.2. • memories: this mandatory abstract feature holds the memories of the block. There are two memo-

ries defined in the block: m_memory that is mandatory and is the output-delaying memory (provides the output value) and the reset_memory that is optional and activated only if the reset_algo_parameter is set to RISING_EDGE, FALLING_EDGE, EITHER or LEVEL as these behavior needs a knowledge of the previous value of the reset_input.

Semantics

The semantics feature is a mandatory abstract feature holding the block semantics variation point spec- ifications. Each semantics variation point is specified through a set of cross tree constraints

• ScalarInput_SimpeDelay: models the basic semantics of the Delay block with only one input port (u_input), the delay value set to 1 and the reset input is deactivated. It is constrained with the (5.6) cross tree constraints.

ScalarInput_SimpleDelay⇒ (ic_scalar_input∨ ic_scalar_parameter) ∧ NONE

reset_input⇔ RISING ∨ FALLING ∨ EITHER ∨ LEVEL ∨ LEVEL_HOLD

reset_memory⇔ RISING∨ FALLING ∨ EITHER ∨ LEVEL

ic_mode_PARAMETER⇔ ic_parameter

ic_mode_input⇔ ic_input

(5.6) • ScalarInput_ListDelay: models the basic semantics of the Delay block with only one input port (u_input), the delay value set to more than one and the reset input is deactivated. It is constrained with the (5.7) cross tree constraints.

ScalarInput_ListDelay⇒ (ic_vector_input∨ ic_vector_parameter) ∧ NONE

reset_input⇔ RISING ∨ FALLING ∨ EITHER ∨ LEVEL ∨ LEVEL_HOLD

reset_memory⇔ RISING∨ FALLING ∨ EITHER ∨ LEVEL

ic_mode_PARAMETER⇔ ic_parameter

ic_mode_input⇔ ic_input

5.5. SPLE FOR THE SPECIFICATION OF BLOCKS

• ScalarInput_SimpleDelay_Reset: models the basic semantics of the Delay block with only one input port (u_input), the delay value set to 1 and the reset input is activated. It is con- strained with the (5.8) cross tree constraints.

ScalarInput_SimpleDelay_Reset⇒ (ic_scalar_input∨ ic_scalar_parameter) ∧ ¬NONE

reset_input⇔ RISING ∨ FALLING ∨ EITHER ∨ LEVEL ∨ LEVEL_HOLD

reset_memory⇔ RISING∨ FALLING ∨ EITHER ∨ LEVEL

ic_mode_PARAMETER⇔ ic_parameter

ic_mode_input⇔ ic_input

(5.8) • ScalarInput_ListDelay_Reset: models the basic semantics of the Delay block with only one input port (u_input), the delay value set to more than 1 and the reset input is activated. It is constrained with the (5.9) cross tree constraints.

ScalarInput_ListDelay_Reset⇒ (ic_vector_input∨ ic_vector_parameter) ∧ ¬NONE

reset_input⇔ RISING ∨ FALLING ∨ EITHER ∨ LEVEL ∨ LEVEL_HOLD

reset_memory⇔ RISING∨ FALLING ∨ EITHER ∨ LEVEL

ic_mode_PARAMETER⇔ ic_parameter

ic_mode_input⇔ ic_input

(5.9) Analysis of the feature model

The product line depicted in Figure 5.42 allows twenty four valid configurations. This number is com- puted based on the number of combinations allowed for the Non-reset semantics (two for each as the only variation is for the initial_condition that is either a parameter or an input), and the resetted semantics that have five combinations (five reset algorithms) and also the two combinations related to the initial_condition. The final number of valid product is then: 2× 2 + (5 × 2) × 2 = 24.

In a block specification oriented reading of the feature model, the number of block variants is less than twenty four as the variability added by the reset_algo parameter can be managed by other means like the definition of a generic function for the reset input impact according to the reset_algo parameter value. The number of valid product can then be limited to eight (two products for each semantics sub- feature).