Static RAM(SRAM) uses between 4 and 6 transistor memory elements for each switch cell9to form a logical unit known as a bistable flip-flop. The flip-flop may be in one of two stable states and, once set in a particular state, and provided the power remains applied, it will continue in that state until a new state is set.Dynamic RAM (DRAM), on the other hand, uses a single transistor-based capacitor10 for each switch cell and the small charge on the capacitor is used to determine its state. As a result of leakage current, however, the charge on each capacitor dissipates quite quickly, and thus has to be refreshed at regular intervals, of the order of a few tens of microseconds or so. It is this characteristic that gives it the namedynamicRAM. Because of the need for this regular refresh, additional circuitry is required, internal addressing is much more complicated and the speed of access is reduced. However, DRAM is much cheaper to manufacture than SRAM, since DRAM requires only one memory element to every six required for SRAM.
These characteristics determine the way in which we use the two kinds of RAM in the PC. Since DRAM is relatively cheap, it is used for the whole of the main RAM memory, which today might be as much as 4 Gbyte. However, since its performance is
Fig. 4.10 The AMD Athlon 64 processor (photograph: Tony Sammes and Brian Jenkinson).
9 IBM uses 6 transistor memory elements for an SRAM cell. See IBM (1997). 10 In IBM DRAM this is known as atrench capacitor. See IBM (1996a).
slow compared with SRAM and it would significantly delay the modern processor, a cache memoryis often provided, the purpose of which is to provide a high-speed buffer between the processor and the slower main memory. In the past, two levels of cache were often found: L1 (or Level 1) SRAM cells built onto the processor chip itself and L2 (Level 2) SRAM chips that were installed on the motherboard. More recently, processors such as the Pentium 4 have contained both L1 and L2 caches on the processor chip itself, and where a further SRAM cache is installed on the mother- board, this is then known as L3 (Level 3) cache.
Memory chips are packaged in many ways. Older chips still use the DIL standard package that we have referred to before, and we may still find some SRAM in sockets on the motherboard in this form. More likely today, however, SRAM will be inPLCC (Plastic Leaded Chip Carrier) orTQFP(Thin Quad Flat Plastic) packages, that are surface mounted onto the motherboard. For the DRAM we may find 100, 168, 184 or 240 pinDIMMs(Dual Inline Memory Modules) or 72, 144 or 200 pinSODIMMs(Small Outline DIMMs) in sockets on the motherboard. Typical memory module sizes currently range from 168 Mbyte to 4 Gbyte, and, as we discussed above, various rules as to the mix of modules permitted are associated with each motherboard. You may recall that our example motherboard of Fig. 4.7 has four 184 pin DDR (Double Data Rate) DIMM sockets. We show an example of a 1 Gbyte 184 pin DIMM memory module at Fig. 4.11.
Advances in the performance of DRAMs have come over the last few years as a result of making changes to the basic DRAM architecture of the chip. The internal layout of a DRAM chip can be likened to that of a spreadsheet with all of its cells in a series of columns and rows. Access to any particular cell may then be made by selecting a specific column and row address.Because of the refresh cycles that have to take place, selecting both the column and the row address takes time. One improvement in the design of the DRAM is to arrange for the rows to have a relatively large number of columns and then to ensure that successive data items are held in the same row. This has the benefit of saving the time needed to select the row address when accessing successive data items, since it already remains selected. Each row can be considered to be a page, and chips using this mode of operation are often called Fast Page Mode(FPM) DRAMs. A further extension to this idea is implemented in Extended Data Out(EDO) DRAMs (IBM, undated). Normally, the cell data is only available while the row and column addresses remain selected. We have seen that with FPM, the row address remains selected between accesses, but clearly the column address cannot if we want to select another element. With EDO, the DRAM holds the data valid on its output pins, even after the column selection has become invalid for the current element and we are starting to access the next element. This speeds up the rate of access and gives an extended period of time over which the processor can
access the data. Clearly the motherboard must be “EDO aware” for this to work. EDO is also sometimes calledHyper Page Mode.
Another advance occurred with the development of Synchronous DRAM (SDRAM) (IBM, 1996b). Where FPM and EDO DRAMs are driven asynchronously, with each access being initiated by control signals from the processor, SDRAM is operated synchronously with all its accesses controlled by the same external clock as that used by the processor. This, together with a burst capability, permits much faster consecutive read and write operations compared with FPM and EDO. In addition, SDRAM may have two internal banks, so that while one bank is being accessed, the other is being prepared.
Double Data Rate(DDR)SDRAMis essentially an improvement over the earlier SDRAM. It is very similar to SDRAM in design and operation, the main difference being that it can transfer data on both the rising and falling edges of a clock cycle. Compared with traditional SDRAM, which can only transfer on the rising edge, this gives DDR SDRAM effectively twice the bandwidth, and by 2005 it had become the mainstream memory technology to be found on most motherboards. From 2003, however, development had started on the next generation of memory,Double Data Rate 2(DDR2)SDRAM, and this improves performance by permitting faster clock rates whilst still maintaining a clean data output. Several motherboards were available at the time of writing which were fitted for DDR2 SDRAM.
Video RAM(VRAM) andSynchronous Graphics RAM(SGRAM) (IBM, 1996c) are DRAMs that have been designed specifically for graphics applications. VRAM is based on the standard asynchronous DRAM architecture, but has the addition of a high-speed serial port and a serial access memory (SAM) that is designed to hold part of a page of data from the internal DRAM array. The VRAM has a standard DRAM interface as well and this permits data to be read from or written to the VRAM whilst serial data is continuously being written to the video interface. Such an approach is sometimes referred to asdual port. SGRAM is video RAM that is very similar in operation to that of SDRAM but has been optimized for graphics-intensive operations. More recently, high-performance graphics cards are beginning to be found withDouble Data Rate 3(DDR3)SDRAMfitted.
ROM
Read-Only Memory(ROM) is characterized by being non-volatile and read-only. The information stored in it may be built into the chip during manufacture or it may be subsequently placed there byprogrammingthe chip. Chips that are capable of being programmed after manufacture are known asProgrammable ROMs(PROMs) and the simplest form is programmed by permanently fusing selected links in the memory chip so that it retains the required binary pattern. This is a one-time process, and such chips cannot be reused.
Reusable read-only memory chips are called Erasable PROMs (EPROMs) or Electrically Erasable PROMs (EEPROMs). EPROMs, together with a later devel- opment known asFlash Memory, are looked at in more detail in Chapter 8, when we consider the significance of the memory type in the treatment of organizers. An example of a Flash EPROM is the BIOS chip seen on the motherboard of Fig. 4.7.