STEP 7 Overwrites Data in the DB
9.3 STARTUP Mode
Before the CPU can start executing the user program, a startup program must first be executed. By programming startup OBs in your startup program, you can specify certain settings for your cyclic program.
There are two types of startup: complete restart and restart (S7-300 CPUs are only capable of a complete restart). A restart is only possible when this is explicitly specified in the parameter record of the CPU using STEP 7.
The features of the STARTUP mode are as follows:
S The program in the startup OB is processed (OB100 for a complete restart and OB101 for a restart)
S No time or interrupt-driven program execution is possible.
S Timers are updated.
S Run-time meters start running.
S Disabled digital outputs on signal modules (can be set by direct access).
A complete restart is always permitted unless the system has requested a memory reset. A complete restart is the only possible option after:
S Memory reset
S Downloading the user program with the CPU in the STOP mode S I stack/B stack overflow
S Complete restart aborted (due to a power outage or changing the mode selector setting)
S When the interruption before a restart exceeds the selected time limit.
A manual complete restart can be triggered by the following:
S The mode selector
The CRST/WRST switch must be set to CRST.
S The corresponding menu on the programming device or by communication functions (mode selector set to RUN or RUN-P).
An automatic complete restart can be triggered following power up in the following situations:
S The CPU was not in the STOP mode when the power outage occurred.
S The mode selector is set to RUN or RUN-P.
S No automatic restart is programmed following power up.
S The CPU was interrupted by a power outage during a complete restart (regardless of the programmed type of restart).
The CRST/WRST switch has no effect on an automatic complete restart.
Features
Complete Restart
Manual Complete Restart
Automatic
Complete Restart
If you operate your CPU without a backup battery (if maintenance-free operation is necessary), the CPU memory is automatically reset and a complete restart executed after the power is turned on or when power returns following a power outage. The user program must be located on a flash EPROM (memory card).
Following a power outage in the RUN mode followed by a return of power, S7-400 CPUs run through an initialization routine and then automatically execute a restart. During a restart, the user program is resumed at the point at which its execution was interrupted. The section of user program that had not been executed before the power outage, is known as the remaining cycle (see also Figure 9-2). The remaining cycle can also contain time and
interrupt-driven program sections.
A restart is only permitted when the user program was not modified in the STOP mode (for example by reloading a modified block) and when there are no other reasons for a complete restart (refer to complete restart). Both a manual and automatic restart are possible.
A manual restart is only possible with the appropriate parameter settings in the parameter record of the CPU and when the STOP resulted from the following causes:
S The mode selector was changed from RUN to STOP.
S The STOP mode was the result of a command from the programming device.
A manual restart can be triggered as follows:
S Using the mode selector.
The CRST/WRST must be set to WRST.
S Using the menu option on the programming device or by communication functions (when the mode selector is set to RUN or RUN-P).
S When a manual restart following power down is set in the parameter record of the CPU.
An automatic restart can be triggered by a power up in the following situations:
S The CPU was not in the STOP mode when the power outage occurred.
S The mode selector is set to RUN or RUN-P.
S Automatic restart following power up is set in the parameter record of the CPU.
The CRST/WRST switch has no effect on an automatic restart.
Automatic
S7-300 and S7-400 CPUs react differently to power up following a power outage.
S7-300 CPUs are only capable of a complete restart. With STEP 7, you can, however, specify memory bits, timers, counters and areas in data blocks as retentive to avoid data loss caused by a power outage. When the power returns, an “automatic complete restart with memory” is executed.
S7-400 CPUs react to the return of power by executing either a complete restart or a restart (depending on the parameter settings).
Tables 9-2 and 9-3 show the data that are retained on S7-300 and S7-400 CPUs during a complete restart or a restart.
X means data retained
0 means data reset or cleared (contents of DBs)
I means data set to the initialization value taken from the EPROM.
Table 9-2 Data Retention in the EPROM Load Memory
EPROM (memory card or integrated)
CPU with backup battery CPU without backup battery
Data Logic
blocks
DB Memory bits, timers, counters
Logic blocks
DB Memory bits, timers,
counters
X X X Only complete restart permitted
Retentive Data Areas Following Power Down
Table 9-3 Data Retention in the RAM Load Memory
RAM (memory card or integrated)
CPU with backup battery CPU without backup battery
Data Logic
blocks
DB Memory bits, timers, counters
Logic blocks
DB Memory bits, timers, counters
X X X Only complete restart permitted
The activities performed by the CPU during startup are illustrated by Table 9-4:
X means is performed
0 means is not performed
Table 9-4 Startup Activities
Activities in Order of Execution In Complete Restart
In Restart
Clear I stack/B stack X 0
Clear non-retentive memory bits, timers, counters X 0
Clear process image output table X selectable
Clear outputs of digital signal modules X selectable
Discard hardware interrupts X 0
Discard diagnostic interrupts X X
Update the system status list (SZL) X X
Evaluate module parameters and transfer to modules or transfer default values
X X
Execution of the relevant startup OB X X
Execute remaining cycle (part of the user program not executed due to the power down)
0 X
Update the process image input table X X
Enable digital outputs (cancel OD signal) X X Startup Activities
If an error occurs during startup, the startup is aborted and the CPU changes to or remains in the STOP mode.
An aborted complete restart must be repeated. After an aborted restart, both a complete restart and a restart are possible.
No startup (complete restart or restart) is executed or it is aborted in the following situations:
S The keyswitch of the CPU is set to STOP.
S A memory reset is requested.
S A memory card with an application identifier that is not permitted for STEP 7 is plugged in (for example STEP 5).
S More than one CPU is plugged in in the single-processor mode.
S If the user program contains an OB that the CPU does not recognize or that has been disabled.
S When, after power up, the CPU recognizes that not all the modules listed in the configuration table created with STEP 7 are actually plugged in.
S If errors occur when evaluating the module parameters.
A restart is not executed or is aborted in the following situations:
S The CPU memory was reset (only a complete restart is possible after memory reset).
S The interruption time limit has been exceeded (this is the time between exiting the RUN mode until the startup OB including the remaining cycle has been executed).
S The module configuration has been changed (for example module replaced).
S The parameter assignment only permits a complete restart.
S When blocks have been loaded, deleted or modified while the CPU was in the STOP mode.
Aborting a Startup
Figure 9-2 shows the activities of the CPU during STARTUP and RUN.
RUN STARTUP
STOP
Complete restart request
Restart request
STOP
Clear PI input/output table, peripheral
I/Os, and non-retentive memory bits, timers, and
counters.
Complete restart OB
Enable the outputs
Restart OB
Remaining cycle
Delete process image output table and peripheral outputs
(selectable)
Interruption time limit exceeded?
Read process image input table
Execute user program
Output process image output table
no yes
Output process image output table
Figure 9-2 CPU Activities in START UP and RUN Sequence of
Activities