Trainer Missile/Launch Pod Assembly
The trainer M/LPA provides training simulation for M/LPA and LP/C loading, handling, and firing. It provides simulation of rocket and missile failures and checks the electrical interface between the trainer M/LPA and the M270 launcher. The major components of the trainer M/LPA are the LP/C structure, the simulator assembly and the interface cables (figure 7-7).
LP/C Structure. The trainer M/LPA structure has the external appearance of the tactical LP/C. The trainer's EB is secured to slide mounts in the aft end of rocket tube number four. The bushings on the bottom of the trainer M/LPA are strengthened to minimize wear from repeated loading and unloading operations.
Simulator Assembly. The simulator assembly contains electronic circuits to simulate weapon types, to simulate failure modes, and to check the electrical interface between the trainer M/LPA and the M270 launcher. It contains one CCA, a trainer harness assembly, two cable connectors, and four front-panel switches (figure 7-8).
Weapon Select Switches. As many as 63 weapon identification codes can be selected using WEAPON switches S3 and S4 on the simulator assembly front panel. Switches S3 and S4 connect the rocket status (RSTAT) lines with the return (RTN) line to generate digital codes. The selected weapon code is communicated over the RSTAT lines to the FCS.
Fault Select Switches. As many as 63 different fault modes can be selected by entering fault codes using FAULT switches S1 and S2 on the simulator assembly front panel. The FAULT switches set the weapon ground power (PWR) lines to indicate the selected fault. The selected fault code is sent through the ground power circuit to the PIM. The PIM provides communications between the trainer M/LPA and the FCS. The FCS reads the fault code from a current-sensing circuit inside the PIM.
Fuze Circuits. The simulator assembly contains six identical fuze circuits. The fuze circuits test the FCS-to-trainer M/LPA interface. They also allow training for warheads using hazes that are set by the FCS fuze-setter module.
Figure 7-8. Simulator Assembly Functional Block Diagram.
The FCS interrogates the desired fuze circuit by applying fuze interrogation signals to the fuze power (VX) line, the monitor (MON) line, and the return (RTN) line. This causes the fuze to send a digital signal back to the FCS indicating the fuze detonation time stored in the fuze circuit memory.
The FCS sets the desired fuze circuit in the simulator assembly from 0.2 to 199.9 seconds detonation time by applying fuze-setting signals to the VX line, the MON line, and the RTN line. The fuze circuit stores the fuze detonation time in nonvolatile memory (memory that retains its contents after power is removed).
The FCS set the desired fuze to the dud condition by applying +29.5 ±2.5 VDC for 250.0 ±10.0 milliseconds between the MON line and the RTN line.
Ground Power Circuits. The simulator assembly contains six identical ground power circuits. The ground power circuits test the ground power (PWR) lines between the FCS and the trainer M/LPA and send the selected fault code to the PIM. Refer to figure 7-9 for ground power circuit operation. The FCS momentarily applies +24 VDC between the ground power (PWR) and ground power return (PWR RTN) lines of the selected ground power channel. This charges a capacitor between the PWR line and the RTN line. Note that the PWR RTN line and the RTN line are connected at the single point ground in the FCS. The metal oxide semiconductor field-effect transistor (MOSFET) is turned on when the FAULT switch is set to close the contacts connected to the appropriate ground power circuit. This allows the capacitor to discharge through the PIM's current-sensing circuit. The PIM's current-sensing circuit produces a fault code, which is read by the FCS computer.
The six ground power circuits are connected as follows:
Circuit 1: W56J2 pin 6 (PWR RTN 1) and W56J2 pin 8 (RTN 1).
Circuit 2: W56J2 pin 14 (PWR RTN 2) and W56J2 pin 16 (RTN 2).
Circuit 3: W56J2 pin 22 (PWR RTN 3) and W56J2 pin 24 (RTN 3).
Circuit 4: W56J2 pin 31 (PWR RTN 4) and W56J2 pin 33 (RTN 4).
Circuit 5: W56J2 pin 39 (PWR RTN 5) and W56J2 pin 41 (RTN 5).
Circuit 6: W56J2 pin 47 (PWR RTN 6) and W56J2 pin 49 (RTN 6).
Guided Missile System Test Set
The guided missile system test set (GMSTS) is a manportable test set that provides the operator with the capability to ascertain the go or no-go condition of the ATACMS missile while it is in the MLP/C. The GMSTS controls power application to the missile, enables communication channels, and downloads and executes missile self-test software. It also reports test results to the operator and provides long-term storage of the results for future analysis. The major components of the GMSTS consist of the test unit, the power supply assembly, and the test accessories kit (figure 7-10).
DC input power to the GMSTS is provided by either a vehicle, using a NATO slave connector supply assembly, a PU-619M motor generator, or the power supply assembly.
Test Unit. The test unit consists of the following assemblies: a standard test equipment-expandable (STE-X) mainframe, a power module assembly, a hardware interface module, a memory module, and a set communicator (SETCOM). The front panel of the test unit is shown in figure 7-11.
STE-X Mainframe. This is a common piece of test equipment presently in the Army inventory The STE-X mainframe, with the appropriate Deep Attack hardware interface module and applications software, is able to communicate, control power, monitor built-in test (BIT) functions, monitor the results of calibration tests, initiate fin motion tests, and determine the overall go or no-go condition of the missile.
Primary input power (+24 VDC) is applied to connector J1 of the STE-X mainframe using cable assembly CX-71.
The STE-X mainframe interfaces at connector J2 with the SETCOM through cable assembly CX-50. Connector J4 provides an interface to a line printer while J3, J5, and J8 are not used during testing of the Deep Attack missile. The mainframe ON/OFF switch (S1) applies input power to the mainframe circuits.
Upon initial application of power the GMSTS automatically initiates a power-up confidence test of the digital circuits in the STE-X mainframe to
ensure that the GMSTS is capable of executing a self-test. If a failure occurs, the fault is displayed in the form of an error code to the operator on the SETCOM. The error code identifies the major malfunctioning assembly. If no fault is found, the system will be initialized.
The STE-X mainframe consists of a master CPU, three slave processors, and memory. The memory consists of 750 K words of nonvolatile reprogrammable mass storage (NRMS) memory, 256 K words of dynamic random access memory (DRAM) and 24 K words of static random access memory (SRAM).
The master CPU is capable of communicating with the missile's inertial guidance unit (IGU) through the hardware interface module's RS-423A data channels. It has direct access to the NRMS and DRAM memory through the main CPU bus. In general, the master CPU provides for the execution and control of all missile testing once it has been supplied with the appropriate Deep Attack software.
Two analog measurement slave processors in the mainframe interface with the analog measurement channels in the hardware interface module for the purpose of voltage sensing. Software monitors the power lines to the missile for undervoltage (+23 VDC) and overvoltage (+30 VDC) or overcurrent (maximum 6.5 amps per channel) conditions. If an undervoltage, overvoltage, or overcurrent condition occurs at the M/LPA interface, the power and communication channels are automatically disconnected. Each slave processor accesses an RS-232 SIO port that allows it to interface with peripheral equipment.
The third slave processor interfaces the SETCOM directly with the main CPU.
Power Module Assembly. The power module assembly accepts +24 VDC input power and provides the required operating voltages (+5 VDC to +60 VDC) for test unit operation.
Hardware Interface Module. The hardware interface module serves as an interface between the STE-X mainframe microprocessor and the Deep Attack missile for the purpose of testing. It is accepted by the mainframe and configures the GMSTS to the specific analog and digital measurement and stimulus requirements of the missile. The hardware interface module consists of a front panel and six CCAs. (See figure 7-12.)
The front panel of the hardware interface module consists of three connectors (J6, J7, and J9), a GMSTS POWER ON indicator (DS2), a MISSILE POWER ON indicator (DS1), an ELAPSED TIME indicator (M1), a MISSILE POWER ENABLE switch (S2), and a MISSILE POWER ENABLE indicator (DS3).
Connector J6 (input power) connects +24 VDC input power to the hardware interface module through cable assembly CX-71P2.
Connector J7 (missile power) connects missile power and test signals to the missile under test through cable assembly CX-70.
Connector J9 (self test) provides a wraparound test circuit for cable assembly CX-70 during the GMSTS self-test.
Cable assembly CX-70P2 connects to this connector.
The GMSTS POWER ON indicator (DS2) indicates that power is applied to the GMSTS.
Figure 7-2. GMSTS Hardware Interface Module CCAs.
The MISSILE POWER ON indicator (DS1) indicates that missile power is available.
The ELAPSED TIME indicator (M1) is a non-resettable total time indicator used to display the total operating hours of the GMSTS.
The MISSILE POWER ENABLE switch (S2) controls missile input power to the hardware interface module.
The MISSILE POWER ENABLE indicator (DS3) indicates that missile input power is applied to the hardware
The RS-423A communications CCA consists of six serial communication channels that serve as an interface between the test unit and the missile. Data transfer between test unit and the missile is across six 3-wire RS-423A serial data channels operating at a rate of 19,200 bps.
Along with serving as a communication link, this CCA also controls the missile power-switching circuits. This control ensures the simultaneous switching of missile power to all channels, thus precluding any one channel from supplying all the current.
This CCA also acknowledges the occurrence of all data transmission interrupts between the missile and the test unit. These include all power status (overcurrent, undervoltage, and overvoltage) interrupt conditions.
Finally, this CCA contains relays to provide isolation between the unused communication channels and the missile. These relays also serve to loop back the outputs of the RS-423A drivers to permit a comprehensive self-test of the CCA during the GMSTS self-self-test operation.
The power-switching CCAs (A1 and A2) are two identical CCAs, each containing three 2-wire power channels.
The power-switching CCAs work together with the power-protection CCA and provide up to six +24 VDC, 4 amp power channels to the missile. Each power channel is monitored for an overcurrent, overvoltage, or undervoltage condition. If a fault condition is sensed, power to the missile is removed.
Four of the six power channels are activated simultaneously during the initial power-up of the missile. These channels are used to power the on-board missile electronics.
The remaining two power lines are activated prior to the initialization of the internal built-in test (IBIT) function, and power is removed upon completion of the test. These power lines supply operational power to the control actuator system (CAS) on board the missile.
The power-protection CCA (A3) is used to monitor the input power to the hardware interface module. If the input power varies below +23 VDC or above +30 VDC, or if the ripple voltage is greater than 4 volts root mean square (RMS), the power-protection CCA (through the power-switching CCAs) will remove power from the missile.
The input analog multiplexer CCAs (A5 and A6) receive analog voltage and current measurement signals from the missile and convert these signals to digital data for use by the STE-X mainframe. They also receive digital data from the mainframe and convert them to analog signals.
Memory Module. The memory module consists of 128 K words of- field-programmable plug-in NRMS memory.
It contains all the software that is required for the main CPU in the STE-X mainframe to test the Deep Attack missile. After it is initially downloaded from the plug-in module, the GMSTS software resides in the mainframe bubble memory (NRMS).
Set Communicator. The SETCOM (figure 7-13) is the interface between the operator and the GMSTS. The front panel displays 72 alphanumeric characters in two lines of 36 characters each. The messages displayed consist of the operator's keyboard entries, step-by-step instructions to the operator, error messages, queries for operator observations, test results displays, and messages
Figure 7-13. GMSTS Set Communicator.
identifying defective assemblies and components within the GMSTS. A numeric keyboard is provided to allow the operator to input test numbers, respond to test step questions, and issue commands to control the test flow.
Digital multimeter capability is also included as part of the SETCOM function with the use of test probe cable
Power Supply Panel. The power supply panel (figure 7-14) converts 110 VAC to 240 VAC, 50 to 400 Hz, input power to +26.4 VDC, 31.4 amps output power for test unit operation and missile testing. The exterior of the panel assembly contains input and output power connectors, an ON/OFF switch, an-d a POWER ON indicator.
The POWER IN connector (J1) is the AC input connector to the power supply panel. The AC power source is routed to connector J1 through the AC primary power cable (CX-72).
The POWER OUT connector (J2) is the DC output connector to the test unit. Connector J2 provides the test unit with +26.4 VDC through the DC power cable (CX-71).
The ON/OFF switch (S1) is a 15-amp circuit breaker that applies the AC input power to the power supply panel.
The POWER ON indicator (DS1) indicates that +26.4 VDC output power is available to the test unit.
Combination Case and Contents. The combination case serves as a storage container for the power supply accessories and the power supply panel. It contains a solar shield, a 115 VAC primary power cable, and a 220 VAC power adapter. The solar shield is a vented aluminum shield that is used as an umbrella to protect the power supply panel from heat and solar radiation. The AC primary power cable assembly (CX-72) is an eight-foot cable that connects the 115 VAC, 60 Hz input power to the power supply panel assembly. The AC power adapter (CA-76) converts the primary power cable (72) to a 240 VAC, 50 Hz configuration. CA-76P1 connects to CX-72P1.
Test Accessories Kit. The test accessories kit contains a solar shield for the STE-X mainframe, a CA-75 NATO slave adapter, cable assemblies CX-70 and CX-71, and a test probe case.