Bit-to-Symbol Mapping

The bit-to-symbol map block converts the serial bit stream into a sequence of multilevel pulses. For 2B1Q, the mapping block takes two bits at the input and produces a sequence of pulses that contain four possible levels. Figure 4.8 shows an example 2B1Q bit mapping taken from ETSI TS 101 135 [7]. In this example, the first bit defines the sign of the output pulse where a one maps to a positive ampli tude pulse and a zero maps into a negative amplitude pulse. The second bit defines the magnitude of the output pulse where a one maps to the lower pulse amplitude and the zero maps to the larger pulse amplitude.

Figure 4.8. Bit-to-symbol mapping in 2B1Q HDSL.

The input bit sequence has a bit rate of R_b bits/sec; the corresponding bit interval is T_b = 1/R_b seconds. Since the mapping block collects two bits for each multi-level symbol, the output symbol interval is twice the bit interval; hence the symbol rate is R_S = 1/2T_b = R_b/2. For 2B1Q, the output symbol rate is one half that of the input bit rate.

For two-pair HDSL in North America [4],[9] and three-pair HDSL in Europe [7],[9], the bit rate on each wire pair is 784 kb/s, and the corresponding symbol rate is 392 kBaud (kSymbols/s). The 3-dB signal bandwidth is 196 kHz.

For two-pair HDSL in Europe transporting a 2.048 Mb/s E1 payload, the line bit rate is 1,168 kb/s on each wire pair, and the corresponding symbol rate is 584 kBaud. The 3-dB signal bandwidth is 292 kHz.

4.1.7 2B1Q Spectral Shaper

The spectral shaper is a low pass filter that shapes the transmit signal spectrum to a form suitable for transmission in loop plant. The 2B1Q transceiver uses a simple spectral shaper, that is, one that provides a fourth order roll-off. The fourth order roll-off is defined via a PSD mask in Section 5.8.4 of the ETSI technical specification on HDSL [7]. Typical implementation of HDSL systems pass a 2B1Q NRZ (non-return to zero) spectrum through a fourth-order Butterworth filter and scale that signal such that the total transmit power is 13.5 dBm.

The HDSL transmit signal power spectral density (PSD) can be mathematically modeled by the following equation:

where f₀ = 392 kHz, f_3dB = 196 kHz, , V_p = 270 Volts, and R = 135 . The above PSD expression models the passing of a rectangular pulse through a fourth order Butterworth filter. The magnitude of the expression is scaled to produce a transmit signal power of 13.5 dBm. Figure 4.9 shows a plot of a nominal HDSL transmit PSD scaled to have a 13.5 dBm transmit power in the interval from 0 to 392 kHz.

Figure 4.9. Nominal 2B1Q HDSL transmit PSD (784 kb/s) with 4th-order roll-off.

Note that for frequencies above the first null at f₀ = 392 kHz, there is still significant energy in the image lobes. This out-of-band energy is important when considering the crosstalk into other systems.

Note that crosstalk coupling to other wire pairs in a cable increases with increasing frequency. A shaping filter with a higher roll-off could further reduce this out-of-band energy, which would reduce the amount of crosstalk into other signals deployed in the cable.

4.1.8 2B1Q HDSL Transceiver Structure

There are numerous ways to build a 2B1Q transceiver. Figure 4.10shows a functional block diagram of an HDSL transceiver supporting the 2B1Q line code. The blocks shown are those that implement the core modem. The top row of blocks implement the transmitter, and the bottom row of blocks implement the receiver function. Because the upstream and downstream channels share the same frequency band, the duplexing function is provided with echo cancellation.

Figure 4.10. Functional block diagram of a 2B1Q HDSL transceiver.

As discussed earlier, the transmitter of the core modem consists of the scrambler^[2], bit-to-symbol mapping, spectral shaping filter, and an analog front end that includes a line driver. The scrambler feeds the bit-to-symbol mapping block that converts the serial bit stream to a sequence of four level pulses as shown in the example of Figure 4.8. The spectral shaper filters the multilevel pulse stream for the bit-to-symbol map block to a spectral shape suitable for transmission on the line. The filter may be implemented with either analog or digital processing. If analog processing is used, then the filtered signal may be fed directly to the line driver. If the filtering is done with digital processing, then the digital-to-analog (D/A) converter converts the digital samples into analog samples, which are then fed to the line driver for transmission on the subscriber line.

[2] The scrambler and descrambler blocks are not shown in the figure; however, the scrambler connects to transmitter input and the receiver output (symbol-to-bit mapper) connects to the descrambler input.

The hybrid circuit provides the four-to-two wire coupling of the transceiver to the subscriber line.

Both the transmitter output and receiver input have two-wire connections to the hybrid circuit. The subscriber line is a single wire pair that transports signals in both directions. A balancing circuit (not shown in the figure) minimizes the leakage of the transmitter output signal into the local receiver input. An ideal hybrid would have no leakage of the local transmit signal into the local receiver, that is, infinite trans-hybrid loss; however, practical hybrids would have around 12 dB of trans-hybrid loss. This amount of trans-hybrid loss allows a significant amount of energy from the local transmitter that must be compensated for in the receiver.

Given that the hybrid circuit is far from an ideal device, the level of the signal leaking from the local transmitter into the local receiver, hereby referred to as the local echo, is typically higher than the level of the desired signal from the far-end transmitter. It is the job of the echo canceler to remove this local echo seen at the receiver input so that information in the desired received signal may be recovered with a high degree of confidence.

For example, let's assume that the subscriber loop attenuates the far-end transmit signal by about 40 dB and the local hybrid circuit has 12 dB of trans-hybrid. Assuming that the transmit signals at both ends of the line each have the same transmit power, then the level of the local echo will be 28 dB higher than the level of the local echo. If for reliable decoding of the desired received signal we desire the level local echo to be 30 dB below the desired received signal, then the echo canceler will need to provide at least 58 dB (28 dB + 30 dB) of echo cancellation. Good echo canceler designs typically provide at least 60 dB of echo cancellation.

As mentioned earlier, the input to the receiver includes the desired receive signal sent from the far-end transmitter across the subscriber line and a local echo resulting from leakage through the hybrid.

The receiver first filters the received signal to remove any unwanted out-of-band noise and automatically adjusts the level of the total received signal, using either an automatic gain control (AGC) circuit or a programmable gain amplifier (PGA), for optimum use of the analog to digital (A/D) converter's dynamic range. Additional digital filtering may then be done on the digitized samples of the received signal.

Prior to recovering the desired signal, the local echo must be removed from the total received filtered signal. At initialization, the echo canceller circuit automatically learns the echo path between the near-end transmitter and near-end receiver. The echo path is that through the shaping filter, transmitter's analog front end, hybrid circuit, the receiver's filters and A/D converter. The

reconstructed echo signal is subtracted from the filtered total receive signal. The receiver then uses a conventional decision feedback equalizer to compensate for the channel impairments, namely loop attenuation and phase distortion, crosstalk, residual echo, and background noise. Finally, the symbol-to-bit mapping block converts the 2B1Q samples to bits, which are then sent to the descrambler.